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    ON-CHIP THROUGH-BODY-VIA CAPACITORS AND TECHNIQUES FOR FORMING SAME
    4.
    发明公开
    ON-CHIP THROUGH-BODY-VIA CAPACITORS AND TECHNIQUES FOR FORMING SAME 审中-公开
    芯片上通过身体威盛电容器和形成相同的技术

    公开(公告)号：EP3311401A1

    公开(公告)日：2018-04-25

    申请号：EP15896494.0

    申请日：2015-06-22

    申请人： Intel Corporation

    发明人： CHEN, Yi Wei ,  PHOA, Kinyip ,  NIDHI, Nidhi ,  LIN, Jui-Yen ,  SHIH, Kun-Huan ,  YANG, Xiaodong ,  HAFEZ, Walid M. ,  TSAI, Curtis

    IPC分类号： H01L21/60

    CPC分类号： H01L23/481 ,  H01L21/76831 ,  H01L21/76898 ,  H01L27/0629 ,  H01L27/1203 ,  H01L28/90 ,  H01L29/945

    摘要： Techniques are disclosed for providing on-chip capacitance using through-body-vias (TBVs). In accordance with some embodiments, a TBV may be formed within a semiconductor layer, and a dielectric layer may be formed between the TBV and the surrounding semiconductor layer. The TBV may serve as one electrode (e.g., anode) of a TBV capacitor, and the dielectric layer may serve as the dielectric body of that TBV capacitor. In some embodiments, the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor. To that end, in some embodiments, the entire semiconductor layer may comprise a low-resistivity material, whereas in some other embodiments, low-resistivity region(s) may be provided just along the sidewalls local to the TBV, for example, by selective doping in those location(s). In other embodiments, a conductive layer formed between the dielectric layer and the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor.

    Capacitor structure
    6.
    发明公开
    Capacitor structure 审中-公开
    Kondensatorstruktur

    公开(公告)号：EP2924730A1

    公开(公告)日：2015-09-30

    申请号：EP14161523.7

    申请日：2014-03-25

    申请人： IPDIA

    发明人： Voiron, Frédéric ,  Tenailleau, Jean-René

    IPC分类号： H01L23/64 ,  H01L29/66 ,  H01L25/065 ,  H01L25/07 ,  H01L49/02 ,  H01L23/522

    CPC分类号： H01L28/91 ,  H01L25/074 ,  H01L28/65 ,  H01L28/75 ,  H01L29/66181 ,  H01L29/945 ,  H01L2224/16145

    摘要： The invention relates to a capacitor structure (2) comprising a silicon substrate (4) with first and second sides (6, 8), a trench capacitor (10) including a basis electrode (12), a multilayer stack comprising at least one of an even elementary sequence of layers and/or one of an odd elementary sequence of layers, wherein an even/odd elementary sequence of layers comprises an insulator layer (16, 20), an even/odd conductive layer (18, 22); and comprising a second pad (26) and a fourth pad (30) coupled to the basis electrode (12), a first pad (24) and a third pad (28) coupled together, the first pad (24) being located on the same substrate side than the second pad (26), the third pad (28) being located on the same substrate side than the fourth pad (30), the third pad (28) being coupled to an even conductive layer (18), said even conductive layer (18) being flush with or protruding from the opposite second side (8).

    摘要翻译： 本发明涉及一种电容器结构（2），包括具有第一和第二侧（6,8）的硅衬底（4），包括基极（12）的沟槽电容器（10），包括至少一个 层的偶数元素序列和/或奇数元素序列之一，其中偶数/奇数元素序列层包括绝缘体层（16,20），偶数/奇数导电层（18,22）; 并且包括耦合到所述基础电极（12）的第二焊盘（26）和第四焊盘（30），耦合在一起的第一焊盘（24）和第三焊盘（28），所述第一焊盘（24） 与第二垫（26）相同的衬底侧，第三衬垫（28）位于与第四衬垫（30）相同的衬底侧上，第三衬垫（28）耦合到均匀导电层（18），所述 偶极导电层（18）与相对的第二侧（8）齐平或突出。

    INTEGRATED CAPACITOR ARRANGEMENT FOR ULTRAHIGH CAPACITANCE VALUES
    8.
    发明公开
    INTEGRATED CAPACITOR ARRANGEMENT FOR ULTRAHIGH CAPACITANCE VALUES 审中-公开
    集成电容器装置，超高容量值

    公开(公告)号：EP1949418A2

    公开(公告)日：2008-07-30

    申请号：EP06821292.7

    申请日：2006-11-02

    申请人： NXP B.V.

    发明人： ROOZEBOOM, Freddy ,  KLOOTWIJK, Johan, H. ,  KEMMEREN, Antonius, L., A., M. ,  REEFMAN, Derk ,  VERHOEVEN, Johannes, F., C., M.

    IPC分类号： H01L21/02

    CPC分类号： H01L28/91 ,  H01L27/0805 ,  H01L27/1087 ,  H01L29/945

    摘要： The present invention relates to an electronic device (300) comprising at least one trench capacitor (302) that can also take the form of an inverse structure, a pillar capacitor. An alternating layer sequence (308) of at least two dielectric layers (312, 316) and at least two electrically conductive layers (314, 318) is provided in the trench capacitor or on the pillar capacitor, such that the at least two electrically conductive layers are electrically isolated from each other and from the substrate by respective ones of the at least two dielectric layers. A set of internal contact pads (332, 334, 340) is provided, and each internal contact pad is connected with a respective one of the electrically conductive layers or with the substrate. By providing an individual internal contact pad for each of the electrically conductive layers, a range of switching opportunities is opened up that allows tuning the specific capacitance of the capacitor to a desired value. The electronic device of the invention thus provides a flexible trench-capacitor manufacturing platform for a multitude of combinations of electrically conductive layers with each other, or, when multiple trenches are used, between electrically conductive layers of different trench capacitors. On-chip applications such as a charge-pump circuit or a DC-to-DC voltage converter are claimed that benefit from the ultra-high capacitance density and the high breakdown voltage that can be achieved with the electronic device of the invention.

    DRAM trench capacitor
    9.
    发明公开
    DRAM trench capacitor 审中-公开
    DRAM Grabenkondensator

    公开(公告)号：EP0967644A2

    公开(公告)日：1999-12-29

    申请号：EP99304812.3

    申请日：1999-06-18

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Schrems, Martin ,  Mandelman, Jack ,  Hoepfener, Joachim ,  Schaefer, Herbert ,  Stengl, Reinhard

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10861 ,  H01L29/945

    摘要： A bottle-shaped trench capacitor having an expanded lower trench portion with an epi layer therein. The epi layer serves as the buried plate of the trench capacitor. A diffusion region surrounds the expanded lower trench portion to enhance the dopant concentration of the epi layer. The diffusion region is formed by, for example, gas phase doping, plasma doping, or plasma immersion ion implantation.

    摘要翻译： 一种瓶形沟槽电容器，其具有在其中具有外延层的扩展的下沟槽部分。 外延层用作沟槽电容器的掩埋板。 扩散区围绕扩展的下沟槽部分以增强外延层的掺杂剂浓度。 扩散区通过例如气相掺杂，等离子体掺杂或等离子体浸入离子注入形成。

    Self aligned buried plate
    10.
    发明公开
    Self aligned buried plate 审中-公开
    Selbstausrichtende vergrabene Schicht

    公开(公告)号：EP0942465A2

    公开(公告)日：1999-09-15

    申请号：EP99103856.3

    申请日：1999-02-27

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Flietner, Bertrand ,  Bergner, Wolfgang

    IPC分类号： H01L21/334 ,  H01L29/94 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10861 ,  H01L27/10829 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

    摘要： A method of forming a buried plate in a silicon substrate uses a silicon substrate having a deep trench etched into the silicon substrate. A highly doped polysilicon layer is formed within the trench. A nitride layer is then formed within the trench over the polysilicon layer. After forming both the polysilicon layer and the nitride layer, both the polysilicon layer and the nitride layer are etched from a certain uppermost portion of the sidewalls of the trench thereby exposing the silicon substrate at the uppermost portions of the sidewalls. After exposing the silicon substrate at the uppermost portions of the sidewalls, a collar oxide layer is formed over the exposed silicon substrate at the uppermost portions of the sidewalls thereby protecting any edges of the polysilicon layer exposed by the etching step.

    摘要翻译： 在硅衬底中形成掩埋板的方法使用在硅衬底中蚀刻有深沟槽的硅衬底。 在沟槽内形成高度掺杂的多晶硅层。 然后在多晶硅层上的沟槽内形成氮化物层。 在形成多晶硅层和氮化物层之后，从沟槽的侧壁的特定最上部蚀刻多晶硅层和氮化物层，从而在侧壁的最上部暴露硅衬底。 在将硅衬底暴露在侧壁的最上部之后，在暴露的硅衬底上在侧壁的最上部形成环状氧化物层，从而保护由蚀刻步骤露出的多晶硅层的任何边缘。