公开(公告)号：EP0632462A3

公开(公告)日：1996-03-27

申请号：EP94303691.3

申请日：1994-05-24

申请人： International Business Machines Corporation

发明人： Sunaga, Toshio

IPC分类号： G11C11/404

CPC分类号： G11C11/404

摘要： A DRAM cell is dislosed which can compensate for the reduction of storage voltage caused by the threshold voltage loss of a cell transistor without using word line boost. The memory cell has a capacitor for charge pumping which is connected to a common junction between a MOS cell transistor and a cell capacitor which are connected in series. The other end of the charge pump capacitor is connected to a control line which is driven during writing so as to boost the storage voltage in the cell capacitor. When the cell transistor is PMOS, the control line is driven by a positive voltage pulse such that the storage voltage for a low level is boosted in negative direction.

公开(公告)号：EP0723268A3

公开(公告)日：1997-07-02

申请号：EP96300133.4

申请日：1996-01-08

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Furuta, Minoru ,  Sunaga, Toshio

IPC分类号： G11C7/00

CPC分类号： G11C7/1018

摘要： A data transfer system for DRAM operates in a burst transfer mode, wherein the OE line is employed to start the burst transfer mode with change of its potential as a start signal. The burst transfer toggles CAS or RAS to synchronize it with data output as if it were a clock signal. This eliminates the necessity to uniquely provide a clock circuit for the DRAM. In addition, OE maintains the function as a switch for determining whether or not data can be output as in the background art by switching the operation mode from the burst transfer mode. Thus, it maintains high compatibility with the conventional DRAM transfer system.

公开(公告)号：EP0632462A2

公开(公告)日：1995-01-04

申请号：EP94303691.3

申请日：1994-05-24

申请人： International Business Machines Corporation

发明人： Sunaga, Toshio

IPC分类号： G11C11/404

CPC分类号： G11C11/404

摘要： A DRAM cell is dislosed which can compensate for the reduction of storage voltage caused by the threshold voltage loss of a cell transistor without using word line boost. The memory cell has a capacitor for charge pumping which is connected to a common junction between a MOS cell transistor and a cell capacitor which are connected in series. The other end of the charge pump capacitor is connected to a control line which is driven during writing so as to boost the storage voltage in the cell capacitor. When the cell transistor is PMOS, the control line is driven by a positive voltage pulse such that the storage voltage for a low level is boosted in negative direction.

摘要翻译： DRAM单元被闭合，其可以补偿由单元晶体管的阈值电压损耗引起的存储电压的降低，而不使用字线增强。 存储单元具有用于电荷泵浦的电容器，其连接到串联连接的MOS单元晶体管和单元电容器之间的公共结。 电荷泵电容器的另一端连接到在写入期间被驱动以控制电池电容器中的存储电压的控制线。 当单元晶体管为PMOS时，控制线由正电压脉冲驱动，使得低电平的存储电压在负方向上升压。

公开(公告)号：EP0595747A3

公开(公告)日：1995-04-26

申请号：EP93480137.4

申请日：1993-09-21

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Dhong, Sang Hoo ,  Shin,Hyun Jong ,  Taira, Yoichi ,  Kirihata, Toshiaki ,  Sunaga, Toshio ,  Terman, Lewis Madison

IPC分类号： G11C11/409

CPC分类号： G11C11/4094

摘要： A sensing technique uses a variable precharge voltage sensing with a single bitline swing in a DRAM cell or array of DRAM cells so that the power dissipation is reduced. The bitline precharge voltage varies from one RAS cycle to the next RAS cycle depending upon the level of the data in the accessed cells. Such an arrangement eliminates the need for a reference voltage generator since the precharge voltage is not the same voltage for each RAS cycle.

摘要翻译： 感测技术在DRAM单元或DRAM单元阵列中使用具有单个位线摆动的可变预充电电压感测，从而降低功耗。 位线预充电电压从一个RAS周期变化到下一个RAS周期，这取决于所访问的单元中的数据的电平。 这样的布置消除了对参考电压发生器的需要，因为预充电电压对于每个RAS周期不是相同的电压。

公开(公告)号：EP0558970A2

公开(公告)日：1993-09-08

申请号：EP93102132.3

申请日：1993-02-11

申请人： International Business Machines Corporation

发明人： Dhong, Sang Hoo ,  Kitamura, Koji ,  Kirihata, Toshiaki ,  Sunaga, Toshio

IPC分类号： G11C11/409 ,  G11C7/06

CPC分类号： G11C11/4091 ,  G11C7/065

摘要： A sensing circuit for dynamic random access memory is disclosed including a pair of bitlines precharged to a first voltage before sensing. A sense amplifier circuit is provided having one node thereof being connected to an external power supply via a switching means including pulsed sense clocks. Control means is provided and is connected to the switching means for controlling the switching means such that the voltage of the power supply is coupled to the node of the sense amplifier for activation for a predetermined period of time, thereby limiting the swing for the high-going bitline to a second voltage lower than said power supply voltage and higher than said first voltage. The reduced bitline swings are achieved by means of the pulsed sense clocks and the pulse widths for sense clocks are determined by means of a reference bitlines connected to the control means.

摘要翻译： 公开了一种用于动态随机存取存储器的感测电路，包括在感测之前预充电到第一电压的一对位线。 提供了一种读出放大器电路，其一个节点通过包括脉冲读出时钟的开关装置连接到外部电源。 提供控制装置并且连接到开关装置，用于控制开关装置，使得电源的电压耦合到读出放大器的节点，以激活预定的时间段，从而限制高电平的摆动， 位于低于所述电源电压并高于所述第一电压的第二电压。 通过脉冲感测时钟来实现减小的位线摆动，并且通过连接到控制装置的参考位线来确定感测时钟的脉冲宽度。

公开(公告)号：EP0558970A3

公开(公告)日：1994-06-01

申请号：EP93102132.3

申请日：1993-02-11

申请人： International Business Machines Corporation

发明人： Dhong, Sang Hoo ,  Kitamura, Koji ,  Kirihata, Toshiaki ,  Sunaga, Toshio

IPC分类号： G11C11/409 ,  G11C7/06

CPC分类号： G11C11/4091 ,  G11C7/065

摘要： A sensing circuit for dynamic random access memory is disclosed including a pair of bitlines precharged to a first voltage before sensing. A sense amplifier circuit is provided having one node thereof being connected to an external power supply via a switching means including pulsed sense clocks. Control means is provided and is connected to the switching means for controlling the switching means such that the voltage of the power supply is coupled to the node of the sense amplifier for activation for a predetermined period of time, thereby limiting the swing for the high-going bitline to a second voltage lower than said power supply voltage and higher than said first voltage. The reduced bitline swings are achieved by means of the pulsed sense clocks and the pulse widths for sense clocks are determined by means of a reference bitlines connected to the control means.

公开(公告)号：EP0595747A2

公开(公告)日：1994-05-04

申请号：EP93480137.4

申请日：1993-09-21

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Dhong, Sang Hoo ,  Shin,Hyun Jong ,  Taira, Yoichi ,  Kirihata, Toshiaki ,  Sunaga, Toshio ,  Terman, Lewis Madison

IPC分类号： G11C11/409

CPC分类号： G11C11/4094

摘要： A sensing technique uses a variable precharge voltage sensing with a single bitline swing in a DRAM cell or array of DRAM cells so that the power dissipation is reduced. The bitline precharge voltage varies from one RAS cycle to the next RAS cycle depending upon the level of the data in the accessed cells. Such an arrangement eliminates the need for a reference voltage generator since the precharge voltage is not the same voltage for each RAS cycle.

摘要翻译： 感测技术在DRAM单元或DRAM单元阵列中使用单个位线摆动的可变预充电电压感测，从而降低功耗。 位线预充电电压根据所访问单元中数据的电平而从RAS周期到下一个RAS周期不等。 这种布置消除了对参考电压发生器的需要，因为每个RAS周期的预充电电压不是相同的电压。

公开(公告)号：EP0833342A3

公开(公告)日：2005-10-26

申请号：EP97307182.2

申请日：1997-09-16

申请人： International Business Machines Corporation

发明人： Watanabe, Shinpei ,  Sunaga, Toshio

IPC分类号： G11C7/00

CPC分类号： G11C7/1021 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/4096

摘要： A DRAM system that can prevent a substantial reduction in bandwidth with respect to a clock pulse frequency even when banks are accessed in no specific order so that a seamless operation is assured not only for reading but also for writing. A prefetch mechanism is used for reading and writing data to a separate memory array at an early stage, so that the activation and precharge operation, which must be performed before reading the next set of data from the memory array, does not affect nor cause any deterioration of access speed. The amount of data prefetched is twice as much as that fetched in the period represented by an array time constant so that in a single bank structure a seamless operation can be performed both for reading and for writing, even when row accesses are performed.

公开(公告)号：EP0833342A2

公开(公告)日：1998-04-01

申请号：EP97307182.2

申请日：1997-09-16

申请人： International Business Machines Corporation

发明人： Watanabe, Shinpei ,  Sunaga, Toshio

IPC分类号： G11C7/00

CPC分类号： G11C7/1021 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/4096

摘要： A DRAM system that can prevent a substantial reduction in bandwidth with respect to a clock pulse frequency even when banks are accessed in no specific order so that a seamless operation is assured not only for reading but also for writing. A prefetch mechanism is used for reading and writing data to a separate memory array at an early stage, so that the activation and precharge operation, which must be performed before reading the next set of data from the memory array, does not affect nor cause any deterioration of access speed. The amount of data prefetched is twice as much as that fetched in the period represented by an array time constant so that in a single bank structure a seamless operation can be performed both for reading and for writing, even when row accesses are performed.

摘要翻译： 即使在没有特定顺序访问存储体的情况下，也可以防止相对于时钟脉冲频率的带宽的显着降低的DRAM系统，从而不仅可以确保无缝操作，而且可以确保读取也可以进行写入。 预取机制用于在早期阶段将数据读取和写入单独的存储器阵列，使得在从存储器阵列读取下一组数据之前必须执行的激活和预充电操作不会影响也不会导致任何 访问速度恶化。 预取的数据量是在由阵列时间常数表示的周期中获取的数据量的两倍，使得在单个存储体结构中，即使执行行访问，也可以执行无缝操作以进行读取和写入。

公开(公告)号：EP0726575A2

公开(公告)日：1996-08-14

申请号：EP96300450.2

申请日：1996-01-23

申请人： International Business Machines Corporation

发明人： Miyatake, Hisatada ,  Sunaga, Toshio ,  Kitamura, Koji ,  Yamamoto, Masaaki

IPC分类号： G11C5/14

CPC分类号： G11C5/14

摘要： A DRAM macro cell 14 integrated together with a logic cell on the same chip comprises a guard ring 26 surrounding the memory forming area, memory cell arrays 42, a power supply line 34, a ground line 36, additional ground lines 38, and by-pass capacitors 70 connected between the power supply line 34 and the ground line 36. The power supply line 34 is connected to a power supply pad different from the power supply pad to which the power supply line of the logic cell is connected, and the ground line 36 and the ground line of the logic cell are connected to common ground pads or proximate grounding pads interconnected by low-impedance lines. The additional ground lines 38 are connected to the substrate to stabilize substrate potential. This provides a high-density semiconductor integrated circuit device which is reliable and enables high-speed operation by forming DRAM macro cells and logic cell on the same chip.

摘要翻译： 与同一芯片上的逻辑单元集成在一起的DRAM宏单元14包括围绕存储器形成区域的保护环26，存储单元阵列42，电源线34，接地线36，附加接地线38， 连接在电源线34和接地线36之间的通过电容器70.电源线34连接到与逻辑单元的电源线连接的电源焊盘不同的电源焊盘，并且接地 线36和逻辑单元的接地线连接到通过低阻抗线互连的公共接地焊盘或邻近的接地焊盘。 附加的接地线38连接到衬底以稳定衬底电位。 这提供了一种高密度半导体集成电路器件，其可靠并且通过在同一芯片上形成DRAM宏单元和逻辑单元来实现高速操作。