公开(公告)号：EP0423933A2

公开(公告)日：1991-04-24

申请号：EP90309934.9

申请日：1990-09-11

申请人： International Business Machines Corporation

发明人： Capps, Louis Bennie ,  Forster, Jimmy Grant ,  Price, William Everett ,  Rupe, Robert William ,  Uplinger, Kenneth Allen

IPC分类号： G06F11/10 ,  G06F11/00

CPC分类号： G06F11/1044 ,  G06F11/073 ,  G06F11/0772

摘要： A personal computer has two memory banks (12,14) respectively connected to two parity check units (16,18) operative to detect parity errors. Upon doing so, each unit (16,18) feeds a parity error signal to a separate latch (22,24). The latches (22,24) are connected to a logic circuit (26) which is in turn connected to an interrupt controller (34) that initiates an interrupt (36) when a parity error occurs. One latch (22) is further connected to a check bit (41) of a register (40) of an I/O port (38) and the check bit (41) is set by the one latch (22). An interrupt handler reads the register and provides messages indicating which memory bank (12,14) caused the parity error.

摘要翻译： 个人计算机具有分别连接到两个奇偶校验单元（16,18）的两个存储器组（12,14），用于检测奇偶校验错误。 在这样做时，每个单元（16,18）将奇偶校验错误信号馈送到单独的锁存器（22,24）。 锁存器（22,24）连接到逻辑电路（26），该逻辑电路又连接到当奇偶校验错误发生时启动中断（36）的中断控制器（34）。 一个锁存器（22）还连接到I / O端口（38）的寄存器（40）的校验位（41），并且校验位（41）由一个锁存器（22）设置。 中断处理程序读取寄存器并提供指示哪个存储器组（12,14）引起奇偶校验错误的消息。

公开(公告)号：EP0423933A3

公开(公告)日：1992-04-08

申请号：EP90309934.9

申请日：1990-09-11

申请人： International Business Machines Corporation

发明人： Capps, Louis Bennie ,  Forster, Jimmy Grant ,  Price, William Everett ,  Rupe, Robert William ,  Uplinger, Kenneth Allen

IPC分类号： G06F11/10 ,  G06F11/00

CPC分类号： G06F11/1044 ,  G06F11/073 ,  G06F11/0772

摘要： A personal computer has two memory banks (12,14) respectively connected to two parity check units (16,18) operative to detect parity errors. Upon doing so, each unit (16,18) feeds a parity error signal to a separate latch (22,24). The latches (22,24) are connected to a logic circuit (26) which is in turn connected to an interrupt controller (34) that initiates an interrupt (36) when a parity error occurs. One latch (22) is further connected to a check bit (41) of a register (40) of an I/O port (38) and the check bit (41) is set by the one latch (22). An interrupt handler reads the register and provides messages indicating which memory bank (12,14) caused the parity error.

公开(公告)号：EP0423933B1

公开(公告)日：1995-04-05

申请号：EP90309934.9

申请日：1990-09-11

申请人： International Business Machines Corporation

发明人： Capps, Louis Bennie ,  Forster, Jimmy Grant ,  Price, William Everett ,  Rupe, Robert William ,  Uplinger, Kenneth Allen

IPC分类号： G06F11/10 ,  G06F11/00

CPC分类号： G06F11/1044 ,  G06F11/073 ,  G06F11/0772

摘要： A personal computer has two memory banks (12,14) respectively connected to two parity check units (16,18) operative to detect parity errors. Upon doing so, each unit (16,18) feeds a parity error signal to a separate latch (22,24). The latches (22,24) are connected to a logic circuit (26) which is in turn connected to an interrupt controller (34) that initiates an interrupt (36) when a parity error occurs. One latch (22) is further connected to a check bit (41) of a register (40) of an I/O port (38) and the check bit (41) is set by the one latch (22). An interrupt handler reads the register and provides messages indicating which memory bank (12,14) caused the parity error.