公开(公告)号：EP0746105A3

公开(公告)日：1997-09-03

申请号：EP96480059.3

申请日：1996-05-07

申请人： International Business Machines Corporation

发明人： Furtek, Frederick Curtis ,  Keyser III, Frank Ray ,  Gould, Scott Whitney ,  Worth, Brian A. ,  Zittritsch, Terrance John

IPC分类号： H03K19/177

CPC分类号： H03K19/1774 ,  H03K19/1737 ,  H03K19/17704

摘要： A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering, and output driver sizing as a function of signal propagation distance.

公开(公告)号：EP0746105A2

公开(公告)日：1996-12-04

申请号：EP96480059.3

申请日：1996-05-07

申请人： International Business Machines Corporation

发明人： Furtek, Frederick Curtis ,  Keyser III, Frank Ray ,  Gould, Scott Whitney ,  Worth, Brian A. ,  Zittritsch, Terrance John

IPC分类号： H03K19/177

CPC分类号： H03K19/1774 ,  H03K19/1737 ,  H03K19/17704

摘要： A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering, and output driver sizing as a function of signal propagation distance.

摘要翻译： 公开了一种用于可编程阵列中的时钟和复位信号分配的信号分配架构。 该架构包括用于将时钟和复位信号分配给阵列的逻辑单元的单独网络。 每个网络包括多个列复用器，用于从多个系统时钟或复位信号中选择列时钟或复位信号。 在逻辑单元的每列中，定位了用于从多个列时钟或复位信号中选择扇区时钟或复位信号的扇区多路复用器。 时钟和复位信号被施加到与给定扇区多路复用器相关联的每个逻辑单元的组合和顺序逻辑电路。 时钟门电路与每个逻辑单元中的输出多路复用器协同控制。 网络被设计为具有最小化信号偏移的特征，包括信号源缓冲，多路复用器信号缓冲以及作为信号传播距离的函数的输出驱动器尺寸。