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    Differential charge sensing system for an integrated memory using dual-capacitance cells coupled to two bit lines
    3.
    发明公开
    Differential charge sensing system for an integrated memory using dual-capacitance cells coupled to two bit lines 失效
    使用双电容双绞线连接的集成存储器的差分充电传感系统

    公开(公告)号：EP0031462A3

    公开(公告)日：1981-08-05

    申请号：EP80107371

    申请日：1980-11-26

    申请人： International Business Machines Corporation

    发明人： Gersbach, John Edwin ,  Kim, Ick Whan ,  Zehle, Adolf Mathias

    IPC分类号： G11C07/00 ,  G11C11/40 ,  G11C11/24

    CPC分类号： G11C11/4026 ,  G11C11/4113 ,  G11C11/413

    摘要： A sensing system is provided for a four device memory cell having first (T16) and second (T18) transistors with first (C3) and second (C4) diffusion capacitances, respectively, storing unequal amounts of charge which are coupled to first (BO) and second (81) bit lines, respectively. The cell is preferably a four device integrated injection logic or merged transistor logic (MTL) bipolar cell. The charges represent stored information and are maintained in a standby condition by maintaining a charge on the bit lines. When the information is to be sensed the bit lines are discharged through the cell to enhance the charge difference in the diffusion capacitances. The charge now stored in the diffusion capacitances is transferred onto the bit lines and detected by a differential sensing circuit (38) connected between the first and second bit lines to which are connected first and second equal valued resistors (R5, R6), respectively. The charge in the diffusion capacitances which results after enhancement may be transferred onto the bit lines by discharging the bit lines through the two resistors or by pulsing up the diffusion capacitances from a terminal remote from the bit lines to force the charge onto the bit lines.

    Differential charge sensing system for a four device MTL memory cell
    6.
    发明公开
    Differential charge sensing system for a four device MTL memory cell 失效
    对于由4份MTL存储器单元的差分电荷读取系统。

    公开(公告)号：EP0031462A2

    公开(公告)日：1981-07-08

    申请号：EP80107371.9

    申请日：1980-11-26

    申请人： International Business Machines Corporation

    发明人： Gersbach, John Edwin ,  Kim, Ick Whan ,  Zehle, Adolf Mathias

    IPC分类号： G11C7/00 ,  G11C11/40 ,  G11C11/24

    CPC分类号： G11C11/4026 ,  G11C11/4113 ,  G11C11/413

    摘要： A sensing system is provided for a four device memory cell having first (T16) and second (T18) transistors with first (C3) and second (C4) diffusion capacitances, respectively, storing unequal amounts of charge which are coupled to first (BO) and second (81) bit lines, respectively. The cell is preferably a four device integrated injection logic or merged transistor logic (MTL) bipolar cell. The charges represent stored information and are maintained in a standby condition by maintaining a charge on the bit lines. When the information is to be sensed the bit lines are discharged through the cell to enhance the charge difference in the diffusion capacitances. The charge now stored in the diffusion capacitances is transferred onto the bit lines and detected by a differential sensing circuit (38) connected between the first and second bit lines to which are connected first and second equal valued resistors (R5, R6), respectively. The charge in the diffusion capacitances which results after enhancement may be transferred onto the bit lines by discharging the bit lines through the two resistors or by pulsing up the diffusion capacitances from a terminal remote from the bit lines to force the charge onto the bit lines.

    Nachladeschaltung für einen Halbleiterspeicher
    7.
    发明公开
    Nachladeschaltung für einen Halbleiterspeicher 失效
    再充电的半导体存储器。

    公开(公告)号：EP0022930A1

    公开(公告)日：1981-01-28

    申请号：EP80103389.5

    申请日：1980-06-18

    申请人： International Business Machines Corporation

    发明人： Heuber, Klaus ,  Wiedmann, Siegfried, Dr.

    IPC分类号： G11C7/00 ,  G11C11/40 ,  G05F3/20

    CPC分类号： G05F3/22 ,  G11C11/4026 ,  G11C11/4113 ,  G11C11/414 ,  G11C11/416

    摘要： Die Nachladeschaltung für einen Halbleiterspeicher mit Speicherzellen aus bipolaren Transistoren und pnp-Lastelementen besteht aus einem als Spannungsquelle mit sehr kleinem Innenwiderstand dienenden Impedanzwandler (2), der mit der Bitreferenzleitung BRL und der Wortreferenzleitung WRL des Halbleiterspeichers verbunden ist und dessen Ausgangsspannung VREFB von einer Gruppe vorgeschalteter Referenzspeicherzellen (1) geregelt ist. Am Eingang des Impedanzwandlers (2) liegt die Zellenreferenzspannung VREFC und an einem Steuereingang (7) ein Steuersignal DA, das den Impedanzwandler (2) während einer Chip-Selektions-Phase deaktiviert. Der Impedanzwandler (2) dient sowohl als Spannungsquelle zur Nachladung als auch zur Erzeugung der Ruhezustandsspannung für den Halbleiterspeicher.

    摘要翻译： 用于具有双极晶体管和PNP负载元件的存储器单元的半导体存储器的再充电包括一个用作与它由一组连接到Bitreferenzleitung BRL和半导体存储器的字基准线WRL和其输出电压VREFB上游一个非常小的内部电阻阻抗变换器（2）的电压源的 基准存储单元（1）被限制。 在阻抗转换器（2），该细胞VREFC参考电压的输入端和一个控制输入端（7），该期间的芯片选择阶段（2）禁止阻抗变换器的控制信号DA。 阻抗转换器（2）既用作用于再充电，以及用于产生用于所述半导体存储器的空闲状态电压的电压源。