公开(公告)号：EP0486148A2

公开(公告)日：1992-05-20

申请号：EP91309011.4

申请日：1991-10-02

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Johnson, Lee Edward, Jr. ,  Kokoszka, Daryl John ,  Larky, Steven Philip ,  Sidoli, Paolo

IPC分类号： G06F9/38

CPC分类号： G06F9/52 ,  G06F9/3824 ,  G06F9/3879

摘要： A data processing system is provided that includes a plurality of processors each including a circuit for providing a busy signal. The system also includes a plurality of registers for storing data wherein each register is dedicated to a selected processor or a selected set of processors. A control circuit is provided for receiving the busy signals and prohibiting storage from an external device to the registers dedicated a processor when that processor provides a busy signal.

摘要翻译： 提供一种数据处理系统，其包括多个处理器，每个处理器包括用于提供繁忙信号的电路。 该系统还包括用于存储数据的多个寄存器，其中每个寄存器专用于所选择的处理器或所选择的一组处理器。 提供控制电路，用于当该处理器提供忙信号时，接收忙信号并禁止从处理器专用于寄存器的存储器。

公开(公告)号：EP0486194A3

公开(公告)日：1994-01-26

申请号：EP91310160.6

申请日：1991-11-04

申请人： International Business Machines Corporation

发明人： Johnson, Lee Edward, Jr. ,  Kokoszka, Daryl John ,  Larky, Steven Philip

IPC分类号： G06F15/72 ,  G06F15/64

CPC分类号： G06T15/005

摘要： A memory system including a circuit for receiving and serially storing a plurality of instructions and a plurality of buffer memories each including a buffer controller 800, 820 for regulating access to that buffer. Also included is a circuit 830, connected to each buffer controller and said receiving circuit, for accessing one or more of said buffers in response to a first serially stored instruction while, in response to at least one other serially stored instruction, accessing at least one remaining buffer.

摘要翻译： 一种存储器系统，包括用于接收并串行存储多个指令的电路和多个缓冲存储器，每个缓冲存储器包括用于调节对该缓冲器的访问的缓冲器控制器800,820。 还包括连接到每个缓冲器控制器和所述接收电路的电路830，用于响应于第一串行存储的指令访问一个或多个所述缓冲器，同时响应于至少一个其他串行存储的指令访问至少一个 剩余缓冲区。

公开(公告)号：EP0486148A3

公开(公告)日：1994-03-09

申请号：EP91309011.4

申请日：1991-10-02

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Johnson, Lee Edward, Jr. ,  Kokoszka, Daryl John ,  Larky, Steven Philip ,  Sidoli, Paolo

IPC分类号： G06F9/38

CPC分类号： G06F9/52 ,  G06F9/3824 ,  G06F9/3879

摘要： A data processing system is provided that includes a plurality of processors each including a circuit for providing a busy signal. The system also includes a plurality of registers for storing data wherein each register is dedicated to a selected processor or a selected set of processors. A control circuit is provided for receiving the busy signals and prohibiting storage from an external device to the registers dedicated a processor when that processor provides a busy signal.

摘要翻译： 提供了一种数据处理系统，其包括多个处理器，每个处理器包括用于提供繁忙信号的电路。 该系统还包括用于存储数据的多个寄存器，其中每个寄存器专用于选择的处理器或选定的一组处理器。 提供控制电路，用于接收忙碌信号，并在该处理器提供忙碌信号时禁止从外部设备存储到专用处理器的寄存器。

公开(公告)号：EP0486194A2

公开(公告)日：1992-05-20

申请号：EP91310160.6

申请日：1991-11-04

申请人： International Business Machines Corporation

发明人： Johnson, Lee Edward, Jr. ,  Kokoszka, Daryl John ,  Larky, Steven Philip

IPC分类号： G06F15/72 ,  G06F15/64

CPC分类号： G06T15/005

摘要： A memory system including a circuit for receiving and serially storing a plurality of instructions and a plurality of buffer memories each including a buffer controller 800, 820 for regulating access to that buffer. Also included is a circuit 830, connected to each buffer controller and said receiving circuit, for accessing one or more of said buffers in response to a first serially stored instruction while, in response to at least one other serially stored instruction, accessing at least one remaining buffer.

摘要翻译： 一种存储器系统，包括用于接收和串行存储多个指令的电路，以及多个缓冲存储器，每个缓冲存储器包括用于调节对该缓冲器的访问的缓冲器控制器800,820。 还包括连接到每个缓冲器控制器和所述接收电路的电路830，用于响应于第一串行存储的指令访问一个或多个所述缓冲器，而响应于至少一个其他串行存储的指令，访问至少一个 剩余缓冲区。