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公开(公告)号：EP0456394B1
公开(公告)日：1995-08-02
申请号：EP91303840.2
申请日：1991-04-26
CPC分类号： G09G5/39 , G06T1/60 , G09G2360/126 , H04N19/423 , H04N19/61
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公开(公告)号：EP0386870A3
公开(公告)日：1992-12-30
申请号：EP90300505.6
申请日：1990-01-18
发明人： West, Roderick Michael , Butler, Nicholas David , Sidoli, Paoli Gerardo , Larky, Steven Philip , Buttimer, Malcolm Douglas , Homewood Brian Clive
IPC分类号： G06F9/46
摘要： In a logic circuit having a plurality of clocked state latches (SRL) and combinatorial logic for functional processing of a task in response to functional clocking C′-B′ of the state latches, the state latches are additionally interconnected to form a scannable chain of latches, and task switching logic 12,14 is provided for suspending task processing by interrupting the functional clocking C′-B′ of the state latches and, during said suspension, for scanning the state latches such that existing contents of the state latches defining a task state can be saved from the state latches and/or new contents defining a task state can be loaded into the state latches. The invention provides an efficient means for switching tasks being performd by a logic circuit in a multiprocessing environment.
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公开(公告)号：EP0486144A2
公开(公告)日：1992-05-20
申请号：EP91308962.9
申请日：1991-09-30
IPC分类号： G06F15/72
CPC分类号： G06T15/80 , G06T15/005
摘要： A graphics processor including an interface 30 for providing triangle primitives representing a graphics image includes a triangle interpolator 310 coupled to the interface for interpolating a triangle primitive and serially computing multiple line primitives from the triangle primitive. A line renderer 320 coupled to the receives a line primitive from the triangle interpolator and provides pixels representing the line primitive while the triangle interpolator is computing another line primitive.
摘要翻译： 包括用于提供表示图形图像的三角形基元的接口30的图形处理器包括耦合到接口的三角形插值器310，用于内插三角形原语并且从三角形原语串行地计算多个线基元。 耦合到从三角形插值器接收线原语的线渲染器320，并且在三角形插值器正在计算另一行原语时提供表示线原语的像素。
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公开(公告)号：EP0386870A2
公开(公告)日：1990-09-12
申请号：EP90300505.6
申请日：1990-01-18
发明人： West, Roderick Michael , Butler, Nicholas David , Sidoli, Paoli Gerardo , Larky, Steven Philip , Buttimer, Malcolm Douglas , Homewood Brian Clive
IPC分类号： G06F9/46
摘要： In a logic circuit having a plurality of clocked state latches (SRL) and combinatorial logic for functional processing of a task in response to functional clocking C′-B′ of the state latches, the state latches are additionally interconnected to form a scannable chain of latches, and task switching logic 12,14 is provided for suspending task processing by interrupting the functional clocking C′-B′ of the state latches and, during said suspension, for scanning the state latches such that existing contents of the state latches defining a task state can be saved from the state latches and/or new contents defining a task state can be loaded into the state latches. The invention provides an efficient means for switching tasks being performd by a logic circuit in a multiprocessing environment.
摘要翻译： 在具有多个时钟状态锁存器（SRL）的逻辑电路和用于响应于状态锁存器的功能时钟C min-B min的功能处理任务的组合逻辑，状态锁存器被附加地互连以形成可扫描链 锁存器和任务切换逻辑12,14用于通过中断状态锁存器的功能时钟C min -B min来中止任务处理，并且在所述暂停期间，用于扫描状态锁存器，使得状态锁存器的现有内容定义为 任务状态可以从状态锁存器和/或定义任务状态的新内容保存到状态锁存器中。 本发明提供了一种用于在多处理环境中切换由逻辑电路执行的任务的有效手段。
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公开(公告)号：EP0359080B1
公开(公告)日：1994-05-11
申请号：EP89116265.3
申请日：1989-09-02
IPC分类号： G09G1/28
CPC分类号： H04N1/648 , G09G3/2051 , G09G5/02
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公开(公告)号：EP0486194A3
公开(公告)日：1994-01-26
申请号：EP91310160.6
申请日：1991-11-04
CPC分类号： G06T15/005
摘要： A memory system including a circuit for receiving and serially storing a plurality of instructions and a plurality of buffer memories each including a buffer controller 800, 820 for regulating access to that buffer. Also included is a circuit 830, connected to each buffer controller and said receiving circuit, for accessing one or more of said buffers in response to a first serially stored instruction while, in response to at least one other serially stored instruction, accessing at least one remaining buffer.
摘要翻译： 一种存储器系统，包括用于接收并串行存储多个指令的电路和多个缓冲存储器，每个缓冲存储器包括用于调节对该缓冲器的访问的缓冲器控制器800,820。 还包括连接到每个缓冲器控制器和所述接收电路的电路830，用于响应于第一串行存储的指令访问一个或多个所述缓冲器，同时响应于至少一个其他串行存储的指令访问至少一个 剩余缓冲区。
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7.发明公开Rasterization processor for a computer graphics system 失效Aufrasterungsprozessorfürgraphische Rechnersysteme。
公开(公告)号：EP0486239A2
公开(公告)日：1992-05-20
申请号：EP91310389.1
申请日：1991-11-11
IPC分类号： G06F15/72
摘要： A graphics processor including an interface for providing triangle primitives and line primitives representing a graphical image, a line drawer for receiving line primitives and for rendering the line primitives, and a triangle interpolator for receiving the triangle primitives from the interface and for providing line primitives therefrom to the line drawer, wherein the interface includes a register for storing graphics image line primitives and for selectively providing the stored line primitives to the line drawer.
摘要翻译： 图形处理器，包括用于提供表示图形图像的三角形图元和线图元的接口，用于接收线图元和用于渲染线图元的线抽屉，以及用于从界面接收三角形图元并用于从其提供线图元的三角形插值器 其中所述接口包括用于存储图形图像线原语的寄存器，并且用于选择性地将所存储的线基元提供给线抽屉。
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公开(公告)号：EP0359080A3
公开(公告)日：1991-08-14
申请号：EP89116265.3
申请日：1989-09-02
IPC分类号： G09G1/28
CPC分类号： H04N1/648 , G09G3/2051 , G09G5/02
摘要： A color display device which includes dither apparatus for each primary color to be displayed. A dither matrix provides a dither signal output as a function of the position of a pixel on the color display device. An input primary color signal includes an integer signal and a fraction signal. The integer signal is incremented by an incrementer. There is means for providing an output primary color signal which is the incremented signal whenever a predetermined relationship exists between the dither signal and the fraction signal, and which is the integer signal whenever the predetermined relationship does not exist.
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公开(公告)号：EP0486148A3
公开(公告)日：1994-03-09
申请号：EP91309011.4
申请日：1991-10-02
IPC分类号： G06F9/38
CPC分类号： G06F9/52 , G06F9/3824 , G06F9/3879
摘要： A data processing system is provided that includes a plurality of processors each including a circuit for providing a busy signal. The system also includes a plurality of registers for storing data wherein each register is dedicated to a selected processor or a selected set of processors. A control circuit is provided for receiving the busy signals and prohibiting storage from an external device to the registers dedicated a processor when that processor provides a busy signal.
摘要翻译： 提供了一种数据处理系统，其包括多个处理器，每个处理器包括用于提供繁忙信号的电路。 该系统还包括用于存储数据的多个寄存器，其中每个寄存器专用于选择的处理器或选定的一组处理器。 提供控制电路，用于接收忙碌信号，并在该处理器提供忙碌信号时禁止从外部设备存储到专用处理器的寄存器。
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公开(公告)号：EP0486194A2
公开(公告)日：1992-05-20
申请号：EP91310160.6
申请日：1991-11-04
CPC分类号： G06T15/005
摘要： A memory system including a circuit for receiving and serially storing a plurality of instructions and a plurality of buffer memories each including a buffer controller 800, 820 for regulating access to that buffer. Also included is a circuit 830, connected to each buffer controller and said receiving circuit, for accessing one or more of said buffers in response to a first serially stored instruction while, in response to at least one other serially stored instruction, accessing at least one remaining buffer.
摘要翻译： 一种存储器系统，包括用于接收和串行存储多个指令的电路，以及多个缓冲存储器，每个缓冲存储器包括用于调节对该缓冲器的访问的缓冲器控制器800,820。 还包括连接到每个缓冲器控制器和所述接收电路的电路830，用于响应于第一串行存储的指令访问一个或多个所述缓冲器，而响应于至少一个其他串行存储的指令，访问至少一个 剩余缓冲区。
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