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    Self timed interface
    1.
    发明公开
    Self timed interface 失效
    Selbstsynchronisierte Schnittstelle

    公开(公告)号：EP0687982A1

    公开(公告)日：1995-12-20

    申请号：EP95101444.8

    申请日：1995-02-03

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Ferraiolo, Frank David ,  Capowski, Robert Stanley ,  Casper, Daniel Francis ,  Jordan, Richard Carroll ,  Laviola, William Constantino

    IPC分类号： G06F13/40 ,  H04L7/033

    CPC分类号： H04L7/0338 ,  G06F13/4256 ,  H04L7/0008

    摘要： A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individualy phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.

    摘要翻译： 自定时接口（STI），其中时钟信号将串行数据时钟位于并行导电总线上，并且时钟信号在总线的单独线路上传输。 总线上每条线上的接收数据与时钟信号相互对齐。 所接收的时钟信号用于为每条线分别定义数据位单元的边界边缘，并且总线的每条线上的数据被单独相位调整，使得例如数据转换位置在单元的中心。

    Method and system for acquiring and maintaining phase synchronism between two digital signals
    2.
    发明公开
    Method and system for acquiring and maintaining phase synchronism between two digital signals 失效
    Phasensynchronismus-Verfahren und -Vorrichtung zwischen zwei digitalen Signalen

    公开(公告)号：EP0692890A1

    公开(公告)日：1996-01-17

    申请号：EP95101349.9

    申请日：1995-02-01

    申请人： International Business Machines Corporation

    发明人： Jordan, Richard Carroll ,  Capowski, Robert Stanley ,  Casper, Daniel Francis ,  Ferraiolo, Frank David ,  Laviola, William Constantino ,  Tomaszewski, Peter Roy

    IPC分类号： H04L7/033

    CPC分类号： H04L7/0338

    摘要： An edge detector has a digital phase locking loop in which one of the signals (e.g., the data signal) is coupled to a delay chain that develops a series of incrementally phase delayed versions of the input. Adjacent phase delayed pairs are selected, one pair at a time, and are compared to the other signal (e.g., the clock signal) to determine if an edge of the clock falls between the edges of the data signal in the selected phase pair, or falls outside the edges of the selected phase pair, on one side or the other thereof. If the clock edge falls outside the selected pair, a control signal selects another pair for comparison and the process is repeated until, for example, the data edges are aligned with the positive going edge of the clock. With a clock frequency equal to twice data frequency, the data can then be sampled on the falling edge of the clock.

    摘要翻译： 边缘检测器具有数字锁相环，其中信号（例如，数据信号）中的一个耦合到延迟链，延迟链产生一系列递增相位延迟的输入版本。 选择相邻相位延迟对，每次一对，并与另一个信号（例如，时钟信号）进行比较，以确定时钟的边沿是否落在所选相位对中数据信号的边沿之间，或 在所选择的相对的边缘之外，在其一侧或另一侧上。 如果时钟沿落在所选择的对之外，则控制信号选择另一对用于比较，并重复处理，直到例如数据沿与时钟的正向边对齐。 在时钟频率等于两倍数据频率的情况下，可以在时钟的下降沿对数据进行采样。