公开(公告)号：EP0366582B1

公开(公告)日：1994-03-09

申请号：EP89480133.1

申请日：1989-09-12

申请人： International Business Machines Corporation

发明人： Grasso, Lawrence Joseph ,  Hoffman, Dale Eugene ,  Morgan, Carrol Eugene ,  Puntar, Charles Albert ,  Young, Diane Kay

IPC分类号： H03K23/50 ,  H03K3/037

CPC分类号： H03K3/0372 ,  H03K23/50

公开(公告)号：EP0366582A3

公开(公告)日：1990-11-07

申请号：EP89480133.1

申请日：1989-09-12

申请人： International Business Machines Corporation

发明人： Grasso, Lawrence Joseph ,  Hoffman, Dale Eugene ,  Morgan, Carrol Eugene ,  Puntar, Charles Albert ,  Young, Diane Kay

IPC分类号： H03K23/50 ,  H03K3/037

CPC分类号： H03K3/0372 ,  H03K23/50

摘要： A high speed counter circuit for counting electrical pulses includes a master/slave flip-flop at the input stage of the counter. An AND gate logically ANDs the pulses being counted with the master output to produce a first gating signal. A plurality of cascade coupled flip-flops each having a slave and an inverse slave output are provided. The clock input to each cascade coupled flip-flop is produced by the logical OR of the electrical pulses being counted, the first gating signal and the slave output of all preceding flip-flops of the counter. The counter output is provided by the inverse slave output of each flip-flop.

公开(公告)号：EP0366582A2

公开(公告)日：1990-05-02

申请号：EP89480133.1

申请日：1989-09-12

申请人： International Business Machines Corporation

发明人： Grasso, Lawrence Joseph ,  Hoffman, Dale Eugene ,  Morgan, Carrol Eugene ,  Puntar, Charles Albert ,  Young, Diane Kay

IPC分类号： H03K23/50 ,  H03K3/037

CPC分类号： H03K3/0372 ,  H03K23/50

摘要： A high speed counter circuit for counting electrical pulses includes a master/slave flip-flop at the input stage of the counter. An AND gate logically ANDs the pulses being counted with the master output to produce a first gating signal. A plurality of cascade coupled flip-flops each having a slave and an inverse slave output are provided. The clock input to each cascade coupled flip-flop is produced by the logical OR of the electrical pulses being counted, the first gating signal and the slave output of all preceding flip-flops of the counter. The counter output is provided by the inverse slave output of each flip-flop.

摘要翻译： 用于计数电脉冲的高速计数器电路包括在计数器的输入级的主/从触发器。 AND门逻辑地将正在计数的脉冲与主输出进行AND运算，以产生第一门控信号。 提供了多个级联耦合的触发器，每个具有从机和从从机输出。 每个级联耦合触发器的时钟输入通过计数的电脉冲，第一选通信号和计数器的所有先前触发器的从输出的逻辑或产生。 计数器输出由每个触发器的反从输出提供。