公开(公告)号：EP0446550A2

公开(公告)日：1991-09-18

申请号：EP90480190.9

申请日：1990-11-27

申请人： International Business Machines Corporation

发明人： Combs, Michael Lee ,  Gruodis, Algirdas Joseph ,  Hoffman, Dale Eugene ,  Puntar, Charles Albert ,  Szabo, Kurt Paul

IPC分类号： G06F11/26

CPC分类号： G01R31/31713 ,  G01R31/31908 ,  G01R31/31919 ,  G01R31/31921 ,  G01R31/31922 ,  G01R31/31924

摘要： Apparatus and method for controlling an operation of a test pin of a per-pin semiconductor device test system [10]. The apparatus includes pattern storage memory [42] for storing and for outputting information related to a state of the test pin for individual ones of a plurality of consecutive test cycles, pattern processor [14] having an input coupled to the pattern storage memory for generating for each of the test cycles words comprised of M bits, and a test pin control memory [18] having an input coupled to the output of the pattern processor for decoding each of the words into 2 M or less command words. Each of the decoded command words includes a plurality of control bits. Predetermined ones of the plurality of control bits are coupled to pin driver electronics [24,28] for specifying, for each of the test cycles, at least one characteristic of an electrical signal transmitted to the test pin. The test system also includes test pin signal receiving circuitry [26] for coupling to the test pin for receiving an electrical signal therefrom. Other predetermined ones of the control bits are coupled to the receiving circuitry for specifying, for each of the test cycles, at least one operating characteristic associated with the receiving circuitry.

摘要翻译： 用于控制每针半导体器件测试系统的测试引脚的操作的装置和方法[10]。 该装置包括用于存储并输出与多个连续测试周期中的各个测试引脚的状态有关的信息的模式存储器[42]，模式处理器[14]具有耦合到模式存储存储器的输入，用于产生 对于每个测试周期由M位组成的字，以及具有耦合到模式处理器的输出的输入的测试引脚控制存储器[18]，用于将每个字解码为2个或更少的命令字。 每个解码的命令字包括多个控制位。 多个控制位中的预定个数被耦合到引脚驱动电路[24,28]，用于在每个测试周期中指定发送到测试引脚的电信号的至少一个特性。 测试系统还包括测试引脚信号接收电路[26]，用于耦合到测试引脚以从其接收电信号。 控制位中的其它预定的位耦合到接收电路，用于为每个测试周期指定与接收电路相关联的至少一个操作特性。

公开(公告)号：EP0366582B1

公开(公告)日：1994-03-09

申请号：EP89480133.1

申请日：1989-09-12

申请人： International Business Machines Corporation

发明人： Grasso, Lawrence Joseph ,  Hoffman, Dale Eugene ,  Morgan, Carrol Eugene ,  Puntar, Charles Albert ,  Young, Diane Kay

IPC分类号： H03K23/50 ,  H03K3/037

CPC分类号： H03K3/0372 ,  H03K23/50

公开(公告)号：EP0286808A2

公开(公告)日：1988-10-19

申请号：EP88102733.8

申请日：1988-02-24

申请人： International Business Machines Corporation

发明人： Gruodis, Algirdas Joseph ,  Hoffman, Dale Eugene ,  Puntar, Charles Albert ,  Skooglund, Daniel Edward

IPC分类号： H03K19/013 ,  H03K19/086 ,  H03K19/003

CPC分类号： H03K19/01831 ,  H03K19/00353

摘要： Disclosed is a method and circuit for reducing and maintaining constant overshoot in a high speed driver. The circuit includes a predriver circuit which is driven single endedly and a driver circuit which is differentially driven by the predriver outputs. The predriver and the driver are differen­tial pairs, with commonly controlled individual transistor current sources. A diode has been added in series with each emitter of the differential pairs. Schottky diodes are preferable because of their low capacitance. The diodes increase the input switching voltage (the smallest input voltage swing that will cause the outputs to fully switch) of the differential pair because they must also be switched on and off. The increase results in an increase in effective transition time, which results in smaller overshoots because the circuit is being switched slower. The output amplitude of the driver is set by a voltage which controls the current source currents of the commonly controlled current sources. As the amplitude is decreased the input switching voltage decreases because the current through the devices decreases which results in smaller base-emitter and diode voltages. Due to the commonly controlled current sources, the predriver amplitude decreases as the driver amplitude decreases. The predriver is designed such that its variable output supplies the driver with the proper input switching voltage at any driver amplitude. This keeps the effective input transition time constant which results in constant output overshoot.

摘要翻译： 公开了一种用于减少和在高速驱动器保持恒定的过冲的方法和电路。 该电路包括预驱动器电路的所有被驱动单端形式和驱动器电路，其全部被差分由预驱动器输出驱动。 预驱动器和驱动器是差分对，与常用控制单独的晶体管的电流源。 二极管已在一系列被添加与差动对每个发射器。 肖特基二极管是由于它们的低电容的优选。 二极管增加输入切换电压（最小输入电压摆动thatwill导致输出到完全切换）的差动对，因为它们必须因此打开和关闭。所述增加导致在有效过渡时间增加了进行切换，这导致 较小的过冲，因为电路正在切换慢。 所述驱动器的输出振幅由它控制的常用控制电流源的电流源电流的电压设定。 作为振幅减小时，输入切换电压减小，因为通过设备跌幅，这导致更小的基极 - 发射极二极管和电压下的电流。 由于通常受控电流源，其幅度减小预驱动器作为驱动振幅减小。 预驱动器被设计检查做它的可变输出提供在任何驱动振幅适当的输入切换电压的驱动程序。 这样可以使有效投入转变的时间常数导致恒定的输出过冲。

公开(公告)号：EP0446550B1

公开(公告)日：1996-05-08

申请号：EP90480190.9

申请日：1990-11-27

申请人： International Business Machines Corporation

发明人： Combs, Michael Lee ,  Gruodis, Algirdas Joseph ,  Hoffman, Dale Eugene ,  Puntar, Charles Albert ,  Szabo, Kurt Paul

IPC分类号： G06F11/26

CPC分类号： G01R31/31713 ,  G01R31/31908 ,  G01R31/31919 ,  G01R31/31921 ,  G01R31/31922 ,  G01R31/31924

摘要： Apparatus and method for controlling an operation of a test pin of a per-pin semiconductor device test system [10]. The apparatus includes pattern storage memory [42] for storing and for outputting information related to a state of the test pin for individual ones of a plurality of consecutive test cycles, pattern processor [14] having an input coupled to the pattern storage memory for generating for each of the test cycles words comprised of M bits, and a test pin control memory [18] having an input coupled to the output of the pattern processor for decoding each of the words into 2 or less command words. Each of the decoded command words includes a plurality of control bits. Predetermined ones of the plurality of control bits are coupled to pin driver electronics [24,28] for specifying, for each of the test cycles, at least one characteristic of an electrical signal transmitted to the test pin. The test system also includes test pin signal receiving circuitry [26] for coupling to the test pin for receiving an electrical signal therefrom. Other predetermined ones of the control bits are coupled to the receiving circuitry for specifying, for each of the test cycles, at least one operating characteristic associated with the receiving circuitry.

公开(公告)号：EP0366582A2

公开(公告)日：1990-05-02

申请号：EP89480133.1

申请日：1989-09-12

申请人： International Business Machines Corporation

发明人： Grasso, Lawrence Joseph ,  Hoffman, Dale Eugene ,  Morgan, Carrol Eugene ,  Puntar, Charles Albert ,  Young, Diane Kay

IPC分类号： H03K23/50 ,  H03K3/037

CPC分类号： H03K3/0372 ,  H03K23/50

摘要： A high speed counter circuit for counting electrical pulses includes a master/slave flip-flop at the input stage of the counter. An AND gate logically ANDs the pulses being counted with the master output to produce a first gating signal. A plurality of cascade coupled flip-flops each having a slave and an inverse slave output are provided. The clock input to each cascade coupled flip-flop is produced by the logical OR of the electrical pulses being counted, the first gating signal and the slave output of all preceding flip-flops of the counter. The counter output is provided by the inverse slave output of each flip-flop.

摘要翻译： 用于计数电脉冲的高速计数器电路包括在计数器的输入级的主/从触发器。 AND门逻辑地将正在计数的脉冲与主输出进行AND运算，以产生第一门控信号。 提供了多个级联耦合的触发器，每个具有从机和从从机输出。 每个级联耦合触发器的时钟输入通过计数的电脉冲，第一选通信号和计数器的所有先前触发器的从输出的逻辑或产生。 计数器输出由每个触发器的反从输出提供。

公开(公告)号：EP0446550A3

公开(公告)日：1992-08-05

申请号：EP90480190.9

申请日：1990-11-27

申请人： International Business Machines Corporation

发明人： Combs, Michael Lee ,  Gruodis, Algirdas Joseph ,  Hoffman, Dale Eugene ,  Puntar, Charles Albert ,  Szabo, Kurt Paul

IPC分类号： G06F11/26

CPC分类号： G01R31/31713 ,  G01R31/31908 ,  G01R31/31919 ,  G01R31/31921 ,  G01R31/31922 ,  G01R31/31924

摘要： Apparatus and method for controlling an operation of a test pin of a per-pin semiconductor device test system [10]. The apparatus includes pattern storage memory [42] for storing and for outputting information related to a state of the test pin for individual ones of a plurality of consecutive test cycles, pattern processor [14] having an input coupled to the pattern storage memory for generating for each of the test cycles words comprised of M bits, and a test pin control memory [18] having an input coupled to the output of the pattern processor for decoding each of the words into 2 M or less command words. Each of the decoded command words includes a plurality of control bits. Predetermined ones of the plurality of control bits are coupled to pin driver electronics [24,28] for specifying, for each of the test cycles, at least one characteristic of an electrical signal transmitted to the test pin. The test system also includes test pin signal receiving circuitry [26] for coupling to the test pin for receiving an electrical signal therefrom. Other predetermined ones of the control bits are coupled to the receiving circuitry for specifying, for each of the test cycles, at least one operating characteristic associated with the receiving circuitry.

公开(公告)号：EP0366582A3

公开(公告)日：1990-11-07

申请号：EP89480133.1

申请日：1989-09-12

申请人： International Business Machines Corporation

发明人： Grasso, Lawrence Joseph ,  Hoffman, Dale Eugene ,  Morgan, Carrol Eugene ,  Puntar, Charles Albert ,  Young, Diane Kay

IPC分类号： H03K23/50 ,  H03K3/037

CPC分类号： H03K3/0372 ,  H03K23/50

摘要： A high speed counter circuit for counting electrical pulses includes a master/slave flip-flop at the input stage of the counter. An AND gate logically ANDs the pulses being counted with the master output to produce a first gating signal. A plurality of cascade coupled flip-flops each having a slave and an inverse slave output are provided. The clock input to each cascade coupled flip-flop is produced by the logical OR of the electrical pulses being counted, the first gating signal and the slave output of all preceding flip-flops of the counter. The counter output is provided by the inverse slave output of each flip-flop.

公开(公告)号：EP0286808A3

公开(公告)日：1990-07-04

申请号：EP88102733.8

申请日：1988-02-24

申请人： International Business Machines Corporation

发明人： Gruodis, Algirdas Joseph ,  Hoffman, Dale Eugene ,  Puntar, Charles Albert ,  Skooglund, Daniel Edward

IPC分类号： H03K19/013 ,  H03K19/086 ,  H03K19/003

CPC分类号： H03K19/01831 ,  H03K19/00353

摘要： Disclosed is a method and circuit for reducing and maintaining constant overshoot in a high speed driver. The circuit includes a predriver circuit which is driven single endedly and a driver circuit which is differentially driven by the predriver outputs. The predriver and the driver are differen­tial pairs, with commonly controlled individual transistor current sources. A diode has been added in series with each emitter of the differential pairs. Schottky diodes are preferable because of their low capacitance. The diodes increase the input switching voltage (the smallest input voltage swing that will cause the outputs to fully switch) of the differential pair because they must also be switched on and off. The increase results in an increase in effective transition time, which results in smaller overshoots because the circuit is being switched slower. The output amplitude of the driver is set by a voltage which controls the current source currents of the commonly controlled current sources. As the amplitude is decreased the input switching voltage decreases because the current through the devices decreases which results in smaller base-emitter and diode voltages. Due to the commonly controlled current sources, the predriver amplitude decreases as the driver amplitude decreases. The predriver is designed such that its variable output supplies the driver with the proper input switching voltage at any driver amplitude. This keeps the effective input transition time constant which results in constant output overshoot.