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公开(公告)号：EP0440332A3
公开(公告)日：1994-01-19
申请号：EP91300076.6
申请日：1991-01-04
IPC分类号： H01L27/02 , H01L27/118
CPC分类号： H01L23/528 , H01L27/11898 , H01L2924/0002 , H01L2924/00
摘要： In accordance with the teachings of this invention a method for positioning components of input/output circuits is provided. These components are positioned on a semiconductor substrate. The semiconductor substrate includes other than input/output circuits. Each input/output circuit is provided for processing a single bit of information within a data word containing multiple bits. The method includes the step of (1) dividing each input/output circuit into groups containing similar functional subcomponents; (2) forming a vertical column of subcomponents for each input/output circuit and connecting these subcomponents to perform the function; (3) placing said columns in adjacency to form a plurality of columns with like subcomponents immediately adjacent to each other forming row groups of said like subcomponents; and (4) forming guard rings around the subcomponent row groups if required. Also in accordance with this invention, a group of input/output circuits is provided. The group is positioned on an integrated circuit substrate that contains other than input/output circuits. The input/output circuits group includes a plurality of columns of circuitry component where each column represents all of the input/output circuit components for processing a single bit of information in a group of bits, a plurality of rows positioned across the columns containing like devices among said input/output circuits, and at least one guard ring containing at least one of the plurality of rows.
摘要翻译： 根据本发明的教导，提供了一种用于定位输入/输出电路的部件的方法。 这些组件位于半导体衬底上。 半导体衬底包括输入/输出电路以外的其他电路。 每个输入/输出电路被提供用于处理包含多个比特的数据字内的单个比特的信息。 该方法包括以下步骤：（1）将每个输入/输出电路分成包含相似功能子组件的组; （2）为每个输入/输出电路形成子组件的垂直列并连接这些子组件以执行该功能; （3）将所述列邻近放置以形成具有彼此直接相邻的相似子组件的多个列，以形成所述相似子组件的行组; 和（4）如果需要，在子组件行周围形成保护环。 同样根据本发明，提供了一组输入/输出电路。 该组位于包含输入/输出电路以外的集成电路基板上。 输入/输出电路组包括多列电路组件，其中每列代表用于处理一组比特中的单个比特的信息的所有输入/输出电路组件，跨过列包含类似设备的多个行 在所述输入/输出电路中，以及包含所述多个行中的至少一个的至少一个保护环。
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公开(公告)号：EP0440332B1
公开(公告)日：1997-12-17
申请号：EP91300076.6
申请日：1991-01-04
IPC分类号： H01L27/02 , H01L27/118
CPC分类号： H01L23/528 , H01L27/11898 , H01L2924/0002 , H01L2924/00
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公开(公告)号：EP0055799A3
公开(公告)日：1982-08-04
申请号：EP81108118
申请日：1981-10-09
IPC分类号： G11C11/00
CPC分类号： G11C14/00
摘要： The non-volatile semiconductor memory includes a one device dynamic volatile memory cell having a storage capacitor (C s ) with a plate (12) and a storage node (10) coupled to a non-volatile device having a floating gate (FG), a control gate (24) and a voltage divider (16) having first and second serially-connected capacitors (C1, C2), with the floating gate (FG) being disposed at the common point between the first and second capacitors. The plate (12) of the storage capacitor is connected to a reference voltage source. The control gate (24) is preferably capacitively coupled to the floating gate (FG) through the first (C1) capacitor which includes a dual charge or electron injector structure (26). The capacitance of the first capacitor (C1) has a value substantially less than that of the second capacitor (C2).
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4.发明公开
公开(公告)号：EP0055799A2
公开(公告)日：1982-07-14
申请号：EP81108118.1
申请日：1981-10-09
IPC分类号： G11C11/00
CPC分类号： G11C14/00
摘要： The non-volatile semiconductor memory includes a one device dynamic volatile memory cell having a storage capacitor (C s ) with a plate (12) and a storage node (10) coupled to a non-volatile device having a floating gate (FG), a control gate (24) and a voltage divider (16) having first and second serially-connected capacitors (C1, C2), with the floating gate (FG) being disposed at the common point between the first and second capacitors. The plate (12) of the storage capacitor is connected to a reference voltage source. The control gate (24) is preferably capacitively coupled to the floating gate (FG) through the first (C1) capacitor which includes a dual charge or electron injector structure (26). The capacitance of the first capacitor (C1) has a value substantially less than that of the second capacitor (C2).
摘要翻译： 非易失性半导体存储器包括具有与板（12）的存储电容器（C5）和耦合到具有浮动栅极（FG）的非易失性器件的存储节点（10）的一个器件动态易失性存储器单元， 控制栅极（24）和具有第一和第二串联电容器（C1，C2）的分压器（16），浮置栅极（FG）设置在第一和第二电容器之间的公共点处。 存储电容器的板（12）连接到参考电压源。 控制栅极（24）优选地通过包括双电荷或电子注入器结构（26）的第一（C1）电容器电容耦合到浮动栅极（FG）。 第一电容器（C1）的电容值大大小于第二电容器（C2）的电容值。
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5.发明授权Saturation-limited bipolar transistor circuit structure and method of making 失效饱和有限的双极晶体管电路结构及其制备方法
公开(公告)号：EP0043007B1
公开(公告)日：1985-10-02
申请号：EP81104441.1
申请日：1981-06-10
IPC分类号： H01L27/06 , H01L29/06 , H03K19/013 , H03K19/088
CPC分类号： H01L21/8226 , H01L27/0772 , H01L27/0821 , H03K19/013 , H03K19/088
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6.发明公开Saturation-limited bipolar transistor circuit structure and method of making 失效饱和有限的双极晶体管电路结构及其制备方法
公开(公告)号：EP0043007A3
公开(公告)日：1982-12-29
申请号：EP81104441
申请日：1981-06-10
IPC分类号： H01L27/06 , H01L29/06 , H03K19/013 , H03K19/088
CPC分类号： H01L21/8226 , H01L27/0772 , H01L27/0821 , H03K19/013 , H03K19/088
摘要： A saturation-limited bipolar transistor device or circuit and a method of making same are provided which includes a merged NPN transistor (T1) and a PNP transistor (P1) structure formed so as to produce denser cells or circuits. A simple process is used to form the structure which includes a double diffused technique for making the PNP transistor (P1). The PNP transistor (P1) has a double diffused emitter-base arrangement wherein the emitter (30) is asymmetrically positioned with respect to the base (26) so as to also serve as a contactforthe base (34) of the NPN transistor (T1). The PNP transistor (P1) limits the input current by bypassing excess current to a silicon semiconductor substrate or chip. The structure includes an N type epitaxial layer (14) formed on an N type subcollector (12) with a P type region (32, 34) provided near the surface of the epitaxial layer (14). The epitaxial layer serves as the NPN collector and as the PNP base contact region. A first N type region (26) is formed through the P type region (32, 34) extending from the surface of the epitaxial layer (14) to the subcollector (12) dividing the P type region into first and second sections (32, 34) which serve as the PNP collector region and the NPN base region, respectively. A second N type region (38) is formed in the second section (34) of the P type region at the surface of the epitaxial layer (14) acting as the NPN emitter and a P+ region (30) is formed in the first N type region (26) at the surface of the epitaxial layer (14) extending into the second section (34) of the P type region which forms the NPN transistor base. This P+ region (30) serves as the PNP emitter and as the NPN base contact.
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公开(公告)号：EP0440332A2
公开(公告)日：1991-08-07
申请号：EP91300076.6
申请日：1991-01-04
IPC分类号： H01L27/02 , H01L27/118
CPC分类号： H01L23/528 , H01L27/11898 , H01L2924/0002 , H01L2924/00
摘要： In accordance with the teachings of this invention a method for positioning components of input/output circuits is provided. These components are positioned on a semiconductor substrate. The semiconductor substrate includes other than input/output circuits. Each input/output circuit is provided for processing a single bit of information within a data word containing multiple bits. The method includes the step of (1) dividing each input/output circuit into groups containing similar functional subcomponents; (2) forming a vertical column of subcomponents for each input/output circuit and connecting these subcomponents to perform the function; (3) placing said columns in adjacency to form a plurality of columns with like subcomponents immediately adjacent to each other forming row groups of said like subcomponents; and (4) forming guard rings around the subcomponent row groups if required.
Also in accordance with this invention, a group of input/output circuits is provided. The group is positioned on an integrated circuit substrate that contains other than input/output circuits. The input/output circuits group includes a plurality of columns of circuitry component where each column represents all of the input/output circuit components for processing a single bit of information in a group of bits, a plurality of rows positioned across the columns containing like devices among said input/output circuits, and at least one guard ring containing at least one of the plurality of rows.摘要翻译： 根据本发明的教导，提供了一种用于定位输入/输出电路的组件的方法。 这些部件位于半导体基板上。 半导体衬底包括输入/输出电路以外的部分。 每个输入/输出电路用于处理包含多个位的数据字中的单个位信息。 该方法包括以下步骤：（1）将每个输入/输出电路分成包含类似功能子部件的组; （2）为每个输入/输出电路形成一个垂直列的子部件，并连接这些子部件来执行该功能; （3）将所述列邻接地形成多个具有相邻副部件的列，形成所述相似子部件的行组; 和（4）如果需要，在副组件行组周围形成保护环。 同样根据本发明，提供了一组输入/输出电路。 该组位于包含输入/输出电路以外的集成电路基板上。 输入/输出电路组包括多列电路组件，其中每列表示用于处理位组中的单个位的信息的所有输入/输出电路组件，跨越包含相同装置的列的多行 在所述输入/输出电路中，以及至少一个保护环包含所述多个行中的至少一个行。
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9.发明公开Saturation-limited bipolar transistor circuit structure and method of making 失效饱和度限定双极晶体管电路的结构和它们的制备方法。
公开(公告)号：EP0043007A2
公开(公告)日：1982-01-06
申请号：EP81104441.1
申请日：1981-06-10
IPC分类号： H01L27/06 , H01L29/06 , H03K19/013 , H03K19/088
CPC分类号： H01L21/8226 , H01L27/0772 , H01L27/0821 , H03K19/013 , H03K19/088
摘要： A saturation-limited bipolar transistor device or circuit and a method of making same are provided which includes a merged NPN transistor (T1) and a PNP transistor (P1) structure formed so as to produce denser cells or circuits. A simple process is used to form the structure which includes a double diffused technique for making the PNP transistor (P1). The PNP transistor (P1) has a double diffused emitter-base arrangement wherein the emitter (30) is asymmetrically positioned with respect to the base (26) so as to also serve as a contactforthe base (34) of the NPN transistor (T1). The PNP transistor (P1) limits the input current by bypassing excess current to a silicon semiconductor substrate or chip. The structure includes an N type epitaxial layer (14) formed on an N type subcollector (12) with a P type region (32, 34) provided near the surface of the epitaxial layer (14). The epitaxial layer serves as the NPN collector and as the PNP base contact region. A first N type region (26) is formed through the P type region (32, 34) extending from the surface of the epitaxial layer (14) to the subcollector (12) dividing the P type region into first and second sections (32, 34) which serve as the PNP collector region and the NPN base region, respectively. A second N type region (38) is formed in the second section (34) of the P type region at the surface of the epitaxial layer (14) acting as the NPN emitter and a P+ region (30) is formed in the first N type region (26) at the surface of the epitaxial layer (14) extending into the second section (34) of the P type region which forms the NPN transistor base. This P+ region (30) serves as the PNP emitter and as the NPN base contact.
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