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22 条记录 (耗时 0.013 秒)

    Field effect transistor read only memory
    2.
    发明公开
    Field effect transistor read only memory 失效
    场效应晶体管-只读存储器。

    公开(公告)号：EP0139923A2

    公开(公告)日：1985-05-08

    申请号：EP84109398.2

    申请日：1984-08-08

    申请人： International Business Machines Corporation

    发明人： Bertin, Claude Louis ,  Kotecha, Harish Narandas

    IPC分类号： G11C17/00

    CPC分类号： G11C17/12 ,  G11C11/56 ,  G11C11/5692 ,  Y10S257/904

    摘要： A resistor personalized memory cell c(MC) consisting of a resistive gate field effect transistor (2). One end of the gate electrode (5) is connected to the memory cell access line (WL2), the other end to one of its source or drain regions (3, 4). The source or drain region (3, 4) not connected to the gate electrode (5) is connected to the memory cell bit line (BL2). Memory cell personalization is accomplished by selecting the resistance of the resistive gate (5). Memory cell data is read by detecting the current flow through the cell, the magnitude of the current flow being proportional to the gate resistance.

    Multiple ROM data state, read/write memory cell
    5.
    发明公开
    Multiple ROM data state, read/write memory cell 失效
    多个ROM数据状态，读/写存储单元

    公开(公告)号：EP0250930A3

    公开(公告)日：1989-11-23

    申请号：EP87108175.8

    申请日：1987-06-05

    申请人： International Business Machines Corporation

    发明人： Bertin, Claude Louis ,  Kotecha, Harish Narandas

    IPC分类号： G11C11/56

    CPC分类号： G11C11/56 ,  G11C7/18 ,  G11C8/14 ,  G11C11/5692 ,  G11C16/08 ,  G11C16/24

    摘要： A read/write memory cell is disclosed in which multiple ROM data states can be stored. Independent sensing of the resistance values of each of two resistors (13, 14) for the storage of multiple ROM data states. The resistors are encompassed in a pair of cross-coupled resistive gate devices (11, 12) forming branch circuits, thereby allowing each branch circuit to control the conduction of current in the other branch circuit. This allows for read/write data storage in flip-flop-like fashion. In addition, since resistive gate devices are used, the ROM data may be programmed during the late stages of manufacturing.

    Non-volatile static semiconductor memory cell
    6.
    发明公开
    Non-volatile static semiconductor memory cell 失效
    非挥发性静电半导体存储单元

    公开(公告)号：EP0048815A3

    公开(公告)日：1983-08-10

    申请号：EP81106438

    申请日：1981-08-19

    申请人： International Business Machines Corporation

    发明人： Kotecha, Harish Narandas

    IPC分类号： G11C11/00

    CPC分类号： H01L27/115 ,  G11C14/00 ,  H01L29/7882 ,  Y10S257/904

    摘要： This invention provides improved non-volatile semiconductor memories which include a volatile latch circuit having data nodes (A, B) and first and second cross-coupled transistors (12, 14), at least one of the transistors has first and second control gates (30,46; 42, 56), a floating gate (24) and an enhanced conduction insulator (48) or dual electron injector structure disposed between the first control gate (30, 46) and the floating gate (24). The second control gate (42, 56) is connected to the storage node (A). A control voltage source (20, 22) is connected to the first control gate (30, 46) for transferring charge between the enhanced conduction insulator or dual electron injector structure (48) and the data node.