公开(公告)号：EP3143622B1

公开(公告)日：2018-10-03

申请号：EP15730011.2

申请日：2015-06-04

申请人： Qualcomm Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

发明人： JUNG, Seong-Ook ,  YANG, Younghwi ,  SONG, Stanley Seungchul ,  YEAP, Choh Fei ,  WANG, Zhongze

IPC分类号： G11C8/14 ,  G11C11/412 ,  G11C11/419 ,  G11C7/20

CPC分类号： G11C11/419 ,  G11C5/02 ,  G11C7/00 ,  G11C7/20 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417

摘要： A static random-access memory (SRAM) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline. The gating transistor is configured to selectively couple a bitline to the first node of the first inverter responsive to a first wordline signal. The first inverter has a second node coupled to a second wordline. The first wordline and the second wordline are each independently controllable.

公开(公告)号：EP3363018A1

公开(公告)日：2018-08-22

申请号：EP16785603.8

申请日：2016-10-04

申请人： Oracle International Corporation

发明人： JEON, Kanghoon ,  XU, Pangjie ,  CHO, Hoyeol ,  SU, Jason, T.

IPC分类号： G11C8/08

CPC分类号： G11C11/417 ,  G11C5/06 ,  G11C5/063 ,  G11C8/08 ,  G11C11/41

摘要： Systems, methods, and other embodiments associated with improving a static noise margin of memory cells by using charge sharing to under-drive a wordline are described. In one embodiment, a system includes power logic to, in response to a memory request, connect a voltage source with a virtual power network to store an electric charge within the virtual power network based on a voltage from the voltage source. The virtual power network includes a network of interconnects that electrically connect a plurality of driver interconnects. The system includes wordline logic to under-drive a requested wordline of a plurality of wordlines by connecting the requested wordline with the virtual power network to share the electric charge stored in the virtual power network with the requested wordline. The wordline logic under-drives a voltage of the requested wordline to be lower than a source voltage provided by the voltage source.

公开(公告)号：EP3311384A1

公开(公告)日：2018-04-25

申请号：EP16812082.2

申请日：2016-04-13

申请人： Adesto Technologies Corporation

发明人： LEWIS, Derric ,  DINH, John ,  INTRATER, Gideon ,  GONZALES, Nathan

IPC分类号： G11C5/14

CPC分类号： G06F3/0625 ,  G06F1/24 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/3296 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/068 ,  G06F13/4282 ,  G06F2213/0016 ,  G11C5/148 ,  G11C11/417 ,  Y02D10/14 ,  Y02D10/151

摘要： A method of controlling an ultra-deep power down (UDPD) mode in a memory device, can include: receiving a write command from a host via an interface; beginning a write operation on the memory device to execute the write command; reading an auto-UDPD (AUDPD) configuration bit from a status register; completing the write operation on the memory device; automatically entering the UDPD mode upon completion of the write operation in response to the AUDPD configuration bit being set; and entering a standby mode upon completion of the write operation in response to the AUDPD configuration bit being cleared.

公开(公告)号：EP3136198A1

公开(公告)日：2017-03-01

申请号：EP16181553.5

申请日：2016-07-27

申请人： NXP USA, Inc.

发明人： Dao, Chris ,  Pietri, Stefano ,  Ren, Juxiang ,  Ruth, Scott

IPC分类号： G05F3/20 ,  G11C11/407 ,  H01L27/02 ,  H03K19/003

CPC分类号： H03K19/00315 ,  G05F3/205 ,  G11C5/146 ,  G11C11/4074 ,  G11C11/417 ,  H01L27/11582 ,  H01L28/00 ,  H03K19/018514 ,  H03K2217/0018

摘要： A substrate bias circuit and method for biasing a substrate are provided. A substrate bias circuit includes a first voltage source, a second voltage source, a diode coupled between the first voltage source and the second voltage source, and a plurality of transistors, each transistor in the plurality of transistors having a substrate terminal. In one example, the first voltage source supplies, via the diode, the substrate terminal of a first transistor of the plurality of transistors during a power-up, and the second voltage source supplies the substrate terminal of the first transistor after the power-up.

摘要翻译： 提供了一种用于偏置衬底的衬底偏置电路和方法。 衬底偏置电路包括第一电压源，第二电压源，耦合在第一电压源和第二电压源之间的二极管以及多个晶体管，多个晶体管中的每个晶体管具有衬底端子。 在一个示例中，第一电压源在上电期间通过二极管提供多个晶体管的第一晶体管的衬底端子，并且第二电压源在上电之后提供第一晶体管的衬底端子 。

公开(公告)号：EP3032540A1

公开(公告)日：2016-06-15

申请号：EP13891121.9

申请日：2013-08-06

申请人： Renesas Electronics Corporation

发明人： NII, Koji

IPC分类号： G11C11/413 ,  G11C11/41 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11

CPC分类号： H01L27/1104 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1116 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a chip that processes image information or the like, a multi-port SRAM is mixed together with a logic circuit such as a digital signal processing circuit. In that case, for example, in case that the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. However, in this configuration, it is obvious that there is a problem, in that while the occupied area of an embedded SRAM is reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. The outline of the present application is that three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.

摘要翻译： 在处理图像信息等的芯片中，多端口SRAM与诸如数字信号处理电路的逻辑电路混合在一起。 在这种情况下，例如，在使用3端口的情况下，1端口可以用作差分写入和读出端口，并且2端口可以用作单端读出专用端口。 然而，在这种配置中，显然存在一个问题，即在嵌入式SRAM的占用面积减小的同时，写入和读出端口的数量仅限于一个，并且与差分读出一样快的读出特性不能 预计在单端读数。 本申请的概要在于，在嵌入式SRAM的存储单元结构中包含三个差分写入和读出端口，例如N阱区域被布置在单元的中心，并且P阱区域 布置在其两侧。

公开(公告)号：EP2973577A2

公开(公告)日：2016-01-20

申请号：EP14722821.7

申请日：2014-03-11

申请人： Qualcomm Incorporated

发明人： SONG, Stanley Seungchul ,  WANG, Zhongze

IPC分类号： G11C11/417 ,  G11C11/413 ,  G11C5/14 ,  G11C7/04

CPC分类号： G11C11/4074 ,  G06F17/5072 ,  G11C5/147 ,  G11C7/04 ,  G11C11/413 ,  G11C11/417

摘要： A method includes measuring a temperature of a sensor associated with a memory array. The method also includes calculating, at a voltage regulating device, an operating voltage based on the temperature and based on fabrication data associated with the memory array. The method further includes regulating, at the voltage regulating device, a voltage provided to the memory array based on the operating voltage.

摘要翻译： 一种方法包括测量与存储器阵列相关联的传感器的温度。 该方法还包括在电压调节装置处基于温度和基于与存储器阵列相关联的制造数据来计算工作电压。 该方法还包括在电压调节装置处基于工作电压调节提供给存储器阵列的电压。

公开(公告)号：EP2118717B1

公开(公告)日：2013-08-21

申请号：EP08728581.3

申请日：2008-01-30

申请人： Oracle America, Inc.

发明人： LIH, Yolin ,  WENDELL, Dennis ,  LIU, Jun ,  FUNG, Daniel ,  BHATIA, Ajay ,  BALASUBRAMANIAN, Shyam

IPC分类号： G11C11/419

CPC分类号： G11C11/419 ,  G11C5/147 ,  G11C11/417

公开(公告)号：EP2133799B1

公开(公告)日：2012-10-03

申请号：EP09163220.8

申请日：2007-05-22

申请人： Rambus Inc.

发明人： Oh, Kyung Suk ,  Shaeffer, Ian P.

IPC分类号： G06F13/40

CPC分类号： H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

摘要： An integrated circuit device having graduated on-die termination. The integrated circuit device includes an input to receive a data signal, and first and second termination circuits. The first termination circuit includes a first load element and a first switch element to switchably couple the first load element to the data signal input. The second termination circuit includes a second load element and a second switch element to switchably couple the second load element to the data signal input.

公开(公告)号：EP2022056B1

公开(公告)日：2011-11-23

申请号：EP07761457.6

申请日：2007-04-27

申请人： Mosaid Technologies Incorporated

发明人： ZAMPAGLIONE, Michael, Anthony ,  TOOHER, Michael

IPC分类号： G11C5/14 ,  G11C11/417

CPC分类号： G11C5/147 ,  G11C11/417 ,  H03K19/0008

摘要： A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of VDD-(1.5*Vth), or maintain 1.5*Vth across the memory cells, where Vth is a threshold voltage of an SRAM memory cell transistor and VDD is a positive supply voltage. By tracking the Vth of the memory cell transistors in the SRAM array, the circuit reduces leakage current while maintaining data integrity. A threshold voltage reference circuit can include one or more memory cell transistors (in parallel), or a specially wired memory cell to track the memory cell transistor threshold voltage. The value of the virtual ground reference voltage can be based on a ratio of feedback chain elements in a multiplier circuit.

公开(公告)号：EP2118900B1

公开(公告)日：2011-08-17

申请号：EP08728583.9

申请日：2008-01-30

申请人： Montalvo Systems, Inc.

发明人： LIH, Yolin ,  BHATIA, Ajay ,  WENDELL, Dennis ,  LIU, Jun ,  FUNG, Daniel ,  BALASUBRAMANIAN, Shyam

IPC分类号： G11C11/419

CPC分类号： G11C11/419 ,  G11C5/147 ,  G11C11/417

摘要： An elastic power header device and methods of operation are provided to improve both the read and write margin of static random access memory (SRAM) cells by increasing read stability, reducing read disturbance and improving the Signal to Noise Margin (SNM) figure of merit. For example, various implementations of an elastic power header device are utilized as programmable resistances to permit the power supply lines to reach a maximum voltage. Allowing the power supply lines to reach the reference voltage allows more flexibility in read margin, write margin and read stability. Furthermore, this additional flexibility can be controlled by means for adjusting a voltage. This adjustment voltage can fine-tune the programmable resistances so that the read margin and the write margin can be more conveniently controlled.