公开(公告)号：EP0492099A2

公开(公告)日：1992-07-01

申请号：EP91118971.0

申请日：1991-11-07

申请人： International Business Machines Corporation

发明人： Hiltebeitel, Nathan Rafael ,  Pontius, Dale Edward ,  Tomashot, Steven William

IPC分类号： G06F11/20

CPC分类号： G11C29/785 ,  G11C29/808

摘要： A download system for programming decoders for redundancy. Auxiliary fuse banks (10, 15) have sets of nonvolatile storage elements, such as fuses that store logic states that (a) select a redundant decoder and (b) indicate the address of a faulty row/column of memory cells (MEMORY MARCO n). When the chip (100) is first powered up, each set of nonvolatile storage elements (10A, 10B, 15A, 15Z) is accessed and downloaded to program selected redundant decoders. Because the sets of nonvolatile storage elements can be dynamically assigned to redundant decoders on an any-for-any basis, the fault tolerance of the redundancy system is enhanced.

摘要翻译： 用于冗余编程解码器的下载系统。 辅助熔丝组（10,15）具有一组非易失性存储元件，例如存储逻辑状态的熔丝，（a）选择冗余解码器和（b）指示存储器单元的错误行/列的地址（MEMORY MARCO n ）。 当芯片（100）首次上电时，访问和下载每组非易失性存储元件（10A，10B，15A，15Z）以编程所选择的冗余解码器。 由于非易失性存储元件的集合可以在任何基础上动态分配给冗余解码器，所以冗余系统的容错能力得到提高。

公开(公告)号：EP0436077A2

公开(公告)日：1991-07-10

申请号：EP90119442.3

申请日：1990-10-10

申请人： International Business Machines Corporation

发明人： Hiltebeitel, Nathan Rafael ,  Tamlyn, Robert ,  Tomashot, Steven William

IPC分类号： G11C11/409

CPC分类号： G11C11/4096

摘要： A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells (10, 20). A first set of multiplexer devices (14, 24) selects one of the two pairs of folded bit lines from each of the arrays (10, 20), and a second set of multiplexer devices (16, 26) selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

摘要翻译： 双端口DRAM，其中单个串行锁存器在来自两个存储器单元阵列（10,20）的两对折叠位线之间共享。 第一组多路复用器装置（14,24）从每个阵列（10,20）中选择两对折叠位线中的一个，并且第二组多路复用器装置（16,26）选择性地将剩余的一个 折叠的位线对到并行端口或串行锁存器以访问串行端口。 这种安排大大降低了芯片业的消费。 同时，通过使用可以在两个操作周期中执行的复制模式，可以实现无限垂直滚动，并且有助于屏蔽写入，同时降低时钟复杂度。

公开(公告)号：EP0335149B1

公开(公告)日：1995-08-16

申请号：EP89104168.3

申请日：1989-03-09

申请人： International Business Machines Corporation

发明人： Fifield, John Atkinson ,  Kalter, Howard Leo ,  Miller, Christopher Paul ,  Tomashot, Steven William

IPC分类号： G06F11/20

CPC分类号： G11C29/84

摘要： A semiconductor memory system in which wordline redundancy is implemented without impacting the access time. A redundant decoder circuit generates a wordline drive inhibit signal which inhibits the generation of a normal wordline signal. Deselection also deselects the normally accessed reference cells, requiring that the redundant cells provide their own reference signal. This last requirement is accomplished by utilization of twin cells for the redundant memory. Placing the redundant memory cells on the sense node side of the bit line isolators enables the effective doubling of the number of redundant cells available for each of a plurality of sub-arrays of a normal memory.

公开(公告)号：EP0514664A2

公开(公告)日：1992-11-25

申请号：EP92106317.8

申请日：1992-04-11

申请人： International Business Machines Corporation

发明人： Hiltebeitel, Nathan Rafael ,  Tamlyn, Robert ,  Tomashot, Steven William ,  Wyckoff, Thomas Walter

IPC分类号： G06F11/20

CPC分类号： G11C29/808 ,  G11C29/818

摘要： An invention is disclosed which implements bit line redundancy in a memory module, such as a dynamic random access memory (DRAM), in accordance with a block write operation. The block write operation is commonly used in dual port RAMs, sometimes referred to as video random access memories (VRAM). Specifically, a block write operation allows a plurality of bits of data to be written to any combination of a plurality of adjacent bit lines defined by a column address. The precise combination of adjacent bit lines selected by the column address is designated by an address mask. The invention provides a memory module with a redundant bit decoder that incorporates the address masking function into the redundant bit decoder during block write operations and also bypasses the masking function during normal read and write operations. This redundant bit decoder allows a single redundant bit line to replace any single defective bit line of the selected group of block write bit lines. It eliminates the need for replacing all the selected bit lines and, thereby, saves silicon area and maximizes the utilization of the available redundant bit elements.

摘要翻译： 公开了根据块写入操作在存储器模块（例如动态随机存取存储器（DRAM））中实现位线冗余的发明。 块写操作通常用在双端口RAM中，有时称为视频随机存取存储器（VRAM）。 具体地，块写入操作允许将多个数据位写入由列地址定义的多个相邻位线的任何组合。 由列地址选择的相邻位线的精确组合由地址掩码指定。 本发明提供一种具有冗余位解码器的存储器模块，其在块写入操作期间将地址掩蔽功能合并到冗余位解码器中，并且在正常读取和写入操作期间绕过掩蔽功能。 该冗余位解码器允许单个冗余位线替代所选择的块写入位线组中的任何单个缺陷位线。 它不需要更换所有选定的位线，从而节省了硅面积并最大限度地利用了可用的冗余位元件。

公开(公告)号：EP0398511A2

公开(公告)日：1990-11-22

申请号：EP90304326.3

申请日：1990-04-23

申请人： International Business Machines Corporation

发明人： Ebbers, Timothy Jon ,  Gupta, Satish ,  Henderson, Randall Lawrence ,  Hiltebeitel, Nathan Rafael ,  Tamlyn, Robert ,  Tomashot, Steven William ,  Williams, Todd

IPC分类号： G11C8/00 ,  G11C7/00 ,  G11C11/409

CPC分类号： G11C7/1075

摘要： In a video random access memory which includes an implementation of a serial access memory register facility which allows the external selection of the portion of the SAM to be scanned out, a control signal is provided which causes the reloading of serial access memory address counter causing the serial scanning to shift from one to another of the serial access memory registers, resulting in an ability to select a stopping point when scanning out of the serial access memory, thereby allowing both the starting and ending points of the data to be scanned out of the serial access memory, to be specified.

摘要翻译： 在一个视频随机存取存储器中，包括一个串行存取存储器寄存器装置的实现，它允许扫描出部分SAM的外部选择，提供一个控制信号，该控制信号导致串行存取存储器地址计数器的重新加载， 串行扫描从串行访问存储器寄存器的一个移位到另一个，从而在从串行访问存储器扫描出来时能够选择停止点，从而允许扫描数据的起始点和结束点 串行存取存储器，待指定。

公开(公告)号：EP0436077B1

公开(公告)日：1996-09-04

申请号：EP90119442.3

申请日：1990-10-10

申请人： International Business Machines Corporation

发明人： Hiltebeitel, Nathan Rafael ,  Tamlyn, Robert ,  Tomashot, Steven William

IPC分类号： G11C11/409

CPC分类号： G11C11/4096

公开(公告)号：EP0398510B1

公开(公告)日：1995-02-08

申请号：EP90304325.5

申请日：1990-04-23

申请人： International Business Machines Corporation

发明人： Gupta, Satish ,  Henderson, Randall Lawrence ,  Hiltebeitel, Nathan Rafael ,  Tamlyn, Robert ,  Tomashot, Steven William ,  Williams, Todd

IPC分类号： G11C8/00 ,  G11C7/00 ,  G11C11/409

CPC分类号： G11C11/4096 ,  G11C7/1075 ,  G11C8/00

公开(公告)号：EP0436077A3

公开(公告)日：1993-05-26

申请号：EP90119442.3

申请日：1990-10-10

申请人： International Business Machines Corporation

发明人： Hiltebeitel, Nathan Rafael ,  Tamlyn, Robert ,  Tomashot, Steven William

IPC分类号： G11C11/409

CPC分类号： G11C11/4096

摘要： A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells (10, 20). A first set of multiplexer devices (14, 24) selects one of the two pairs of folded bit lines from each of the arrays (10, 20), and a second set of multiplexer devices (16, 26) selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

公开(公告)号：EP0335149A3

公开(公告)日：1991-03-20

申请号：EP89104168.3

申请日：1989-03-09

申请人： International Business Machines Corporation

发明人： Fifield, John Atkinson ,  Kalter, Howard Leo ,  Miller, Christopher Paul ,  Tomashot, Steven William

IPC分类号： G06F11/20

CPC分类号： G11C29/84

摘要： A semiconductor memory system in which wordline redundancy is implemented without impacting the access time. A redundant decoder circuit generates a wordline drive inhibit signal which inhibits the generation of a normal wordline signal. Deselection also deselects the normally accessed reference cells, requiring that the redundant cells provide their own reference signal. This last requirement is accomplished by utilization of twin cells for the redundant memory. Placing the redundant memory cells on the sense node side of the bit line isolators enables the effective doubling of the number of redundant cells available for each of a plurality of sub-arrays of a normal memory.

公开(公告)号：EP0335149A2

公开(公告)日：1989-10-04

申请号：EP89104168.3

申请日：1989-03-09

申请人： International Business Machines Corporation

发明人： Fifield, John Atkinson ,  Kalter, Howard Leo ,  Miller, Christopher Paul ,  Tomashot, Steven William

IPC分类号： G06F11/20

CPC分类号： G11C29/84

摘要： A semiconductor memory system in which wordline redundancy is implemented without impacting the access time. A redundant decoder circuit generates a wordline drive inhibit signal which inhibits the generation of a normal wordline signal. Deselection also deselects the normally accessed reference cells, requiring that the redundant cells provide their own reference signal. This last requirement is accomplished by utilization of twin cells for the redundant memory. Placing the redundant memory cells on the sense node side of the bit line isolators enables the effective doubling of the number of redundant cells available for each of a plurality of sub-arrays of a normal memory.

摘要翻译： 实现字线冗余而不影响访问时间的半导体存储器系统。 冗余解码器电路产生禁止产生正常字线信号的字线驱动禁止信号。 取消选择还取消选择正常访问的参考单元，要求冗余单元提供自己的参考信号。 最后一个要求是通过利用双电池来实现冗余存储器。 将冗余存储器单元放置在位线隔离器的感测节点侧使得可以有效地加倍可用于正常存储器的多个子阵列中的每一个的冗余单元。