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公开(公告)号：EP0487819A3
公开(公告)日：1992-12-30
申请号：EP91109300.3
申请日：1991-06-06
IPC分类号： G11C7/00
CPC分类号： G11C7/1075 , G11C11/4096
摘要： A video random access memory (VRAM) includes a dynamic random access memory (DRAM) array and a serial access memory (SAM) connected to bi-directional random and serial ports. The SAM provides the capability for partial but aligned data transfer or mask write back of data from an external source for subsequent partial write operations in the DRAM array. These sources include color registers, on-chip arithmetic logic unit (ALU) output, or the random port. Partial but aligned transfers from the SAM to the DRAM array are accomplished by a data transfer into a selected row between two specified column addresses of the DRAM array. Alternatively, a masked write back into a row of the DRAM array is based on mask register contents. Improved serial access memory data input operation for DRAM array is accomplished by means of a source of "0s" or "1s" for a clear operation, providing a page mode fill from the RAM port or an on-chip ALU, and providing a color register load or based on random port input data. In addition, the use of a mask register for partial write back into a row also enhances serial access memory data input operations to the DRAM array. In one modification, a second SAM connected to a second bi-directional serial port is provided. The second SAM is connected to the first SAM to transfer data therebetween in parallel.
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公开(公告)号：EP0338416A3
公开(公告)日：1991-12-11
申请号：EP89106573.2
申请日：1989-04-13
CPC分类号： G09G5/36 , G06F12/08 , G06F12/1081 , G09G5/14 , G09G5/39
摘要： A display control means such as a virtual display adapter (110) allows the advanced functions of a display controller to be utilized in a large area of memory in addition to the normal use in display memory (120). This large area of memory includes system memory (130), and efficient access to this large area of memory is permitted for normal system use. The display controller also functions with non-contiguous and non-resident bitmaps. The flexibility of demand-paged virtual memory is utilized for display tasks, as display bitmaps may be written to the large area of memory as well as the display memory.
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公开(公告)号：EP0149757A2
公开(公告)日：1985-07-31
申请号：EP84114280.5
申请日：1984-11-27
CPC分类号： G11C7/1006 , G09G1/02
摘要： The system includes a plurality of digital memory units (20, 22,...50) each for storing a plurality of independently addressable binary bits. The units operate together in response to each common bit address to supply a bit from each unit to form an array of bits for a discrete section of a larger array. The units are interconnected through common interconnection buses (e.g. 128, 140) and selective controls (134, 136) to input and output gate connections (e.g. 126, 138) to those buses to provide for selective shifting of bits between units to change the bit array.
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公开(公告)号：EP0756278B1
公开(公告)日：2001-09-26
申请号：EP96305206.3
申请日：1996-07-16
发明人： Gupta, Satish , Maruyama, Kiyoshi , Millman, Steven Edward , Yue, Chung-Wai , Bakoglu, Halil Burhan
CPC分类号： G11B19/02 , G11B27/002 , G11B27/105 , G11B27/11 , G11B27/34 , G11B31/00 , G11B33/10 , G11B2220/20 , G11B2220/213 , G11B2220/2512 , G11B2220/2545 , G11B2220/41 , G11B2220/65
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公开(公告)号：EP0214547B1
公开(公告)日：1993-11-10
申请号：EP86111769.5
申请日：1986-08-26
发明人： Gupta, Satish , Lucas, Bruce David
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6.发明公开Video random access memory with fast, alligned clear and copy 失效视频RAM mit schnellenRücksetzungundKopiermöglichkeit。
公开(公告)号：EP0487819A2
公开(公告)日：1992-06-03
申请号：EP91109300.3
申请日：1991-06-06
IPC分类号： G11C7/00
CPC分类号： G11C7/1075 , G11C11/4096
摘要： A video random access memory (VRAM) includes a dynamic random access memory (DRAM) array and a serial access memory (SAM) connected to bi-directional random and serial ports. The SAM provides the capability for partial but aligned data transfer or mask write back of data from an external source for subsequent partial write operations in the DRAM array. These sources include color registers, on-chip arithmetic logic unit (ALU) output, or the random port. Partial but aligned transfers from the SAM to the DRAM array are accomplished by a data transfer into a selected row between two specified column addresses of the DRAM array. Alternatively, a masked write back into a row of the DRAM array is based on mask register contents. Improved serial access memory data input operation for DRAM array is accomplished by means of a source of "0s" or "1s" for a clear operation, providing a page mode fill from the RAM port or an on-chip ALU, and providing a color register load or based on random port input data. In addition, the use of a mask register for partial write back into a row also enhances serial access memory data input operations to the DRAM array. In one modification, a second SAM connected to a second bi-directional serial port is provided. The second SAM is connected to the first SAM to transfer data therebetween in parallel.
摘要翻译： 视频随机存取存储器（VRAM）包括动态随机存取存储器（DRAM）阵列和连接到双向随机和串行端口的串行存取存储器（SAM）。 SAM提供了用于部分但对齐的数据传输或从外部源屏蔽写入数据以用于DRAM阵列中的后续部分写入操作的能力。 这些源包括彩色寄存器，片上算术逻辑单元（ALU）输出或随机端口。 通过将数据传输到DRAM阵列的两个指定列地址之间的选定行来实现从SAM到DRAM阵列的部分但对准的传送。 或者，屏蔽寄存器内容中的屏蔽写回到DRAM阵列的行中。 DRAM阵列的改进的串行访问存储器数据输入操作是通过清零操作的“0s”或“1s”来实现的，从RAM端口或片上ALU提供页面模式填充，并提供一种颜色 寄存器加载或基于随机端口输入数据。 另外，使用掩模寄存器部分写回到行还可以增强对DRAM阵列的串行访问存储器数据输入操作。 在一个修改中，提供了连接到第二双向串行端口的第二SAM。 第二SAM连接到第一SAM并行传输数据。
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公开(公告)号：EP0487819B1
公开(公告)日：1997-03-05
申请号：EP91109300.3
申请日：1991-06-06
IPC分类号： G11C7/00 , G11C11/409
CPC分类号： G11C7/1075 , G11C11/4096
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公开(公告)号：EP0398510B1
公开(公告)日：1995-02-08
申请号：EP90304325.5
申请日：1990-04-23
发明人： Gupta, Satish , Henderson, Randall Lawrence , Hiltebeitel, Nathan Rafael , Tamlyn, Robert , Tomashot, Steven William , Williams, Todd
IPC分类号： G11C8/00 , G11C7/00 , G11C11/409
CPC分类号： G11C11/4096 , G11C7/1075 , G11C8/00
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公开(公告)号：EP0338416A2
公开(公告)日：1989-10-25
申请号：EP89106573.2
申请日：1989-04-13
CPC分类号： G09G5/36 , G06F12/08 , G06F12/1081 , G09G5/14 , G09G5/39
摘要： A display control means such as a virtual display adapter (110) allows the advanced functions of a display controller to be utilized in a large area of memory in addition to the normal use in display memory (120). This large area of memory includes system memory (130), and efficient access to this large area of memory is permitted for normal system use. The display controller also functions with non-contiguous and non-resident bitmaps. The flexibility of demand-paged virtual memory is utilized for display tasks, as display bitmaps may be written to the large area of memory as well as the display memory.
摘要翻译： 除了在显示存储器（120）中的正常使用之外，诸如虚拟显示适配器（110）的显示控制装置允许显示控制器的高级功能在大面积存储器中被利用。 这种大面积的存储器包括系统存储器（130），并且允许对该大面积存储器的有效访问用于正常的系统使用。 显示控制器还具有非连续和非驻留位图功能。 需求分页虚拟内存的灵活性被用于显示任务，因为显示位图可能被写入大面积的存储器以及显示存储器。
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公开(公告)号：EP0149757A3
公开(公告)日：1988-12-14
申请号：EP84114280
申请日：1984-11-27
CPC分类号： G11C7/1006 , G09G1/02
摘要： The system includes a plurality of digital memory units (20, 22,...50) each for storing a plurality of independently addressable binary bits. The units operate together in response to each common bit address to supply a bit from each unit to form an array of bits for a discrete section of a larger array. The units are interconnected through common interconnection buses (e.g. 128, 140) and selective controls (134, 136) to input and output gate connections (e.g. 126, 138) to those buses to provide for selective shifting of bits between units to change the bit array.
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