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1.发明公开
公开(公告)号：EP0039393A3
公开(公告)日：1983-07-27
申请号：EP81101634
申请日：1981-03-06
Applicant: International Business Machines Corporation
Inventor： Hanft, Roy Francis , Pechanek, Gerald George
CPC classification number: B41J5/46
Abstract: A text recorder of the type which includes a text display device (21) to record text in intelligible form on a typewritten page or line or page-like display in response to character and function identifying signals, a keyboard (20) with a plurality of alphabetic, numeric, symbol and function keys for actuation by an operator to produce a keyboard signal unique to the ectuated key, decoding means (50) responsive to keyboard signals from said keyboard (20) to produce character and function identifying signals and wherein the decoding means (50) includes a word completion means (52) for producing one of at least two groups of one or more character identifying signals (53G) in response to actuation of a selected key on said keyboard (20). each group of character identifying signals representing a different word ending and wherein the word completion means (52) includes means (52 A-B-C) for selecting among the group dependent upon the identity of one or more keys actuated prior to actuation of the selected key.
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2.发明公开Multi-character display controller for text recorder 失效Überwachungsvorrichtungmit Anzeige mehrerer SchreibzeichenfüreinTextregistriergerät。
公开(公告)号：EP0031446A2
公开(公告)日：1981-07-08
申请号：EP80107212.5
申请日：1980-11-20
Applicant: International Business Machines Corporation
Inventor： Hanft, Roy Francis , Pechanek, Gerald George
CPC classification number: B41J7/90 , B41J5/46 , G06F17/276
Abstract: A text recorder includes a multi-character display controller which is operated in a multi-character mode to record (e.g., print on paper or generate a CRT or the like display, (21)) multi-character sequences in response to an operator actuation of a single key of a keyboard (20). Operator actuation of a key generates a coded signal representative of the actuated key, but in the multi-character mode, the normal text recorder function of printing or displaying the character associated with the key is inhibited, and instead, a memory device (8, 10) is accessed which has stored at a location corresponding to the actuated key, a sequence of coded signals representative of a plurality of character, functions or both. The storage device (10) may include a plurality of set of stored signal sequences representing a plurality of multi-character sequences.-The selection between the different storage sets is effected based on a particular key or key sequence previously actuated. The invention is applicable to text recorders designed for use with English or other languages.
Abstract translation: 文本记录器包括多字符显示控制器，其以多字符模式操作以响应于操作者致动记录（例如，在纸张上打印或生成CRT或类似显示器，（21））多字符序列 键（20）的单键。 键的操作者致动产生代表致动键的编码信号，但是在多字符模式中，打印或显示与该键相关联的字符的通常文本记录器功能被禁止，相反，存储器件（8， 10）被存储在与激活的键对应的位置处，表示多个字符，功能或两者的编码信号序列。 存储设备（10）可以包括表示多个多字符序列的多组存储的信号序列。 基于先前激活的特定键或键序列来实现不同存储组之间的选择。 本发明适用于以英文或其他语言使用的文本记录器。
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公开(公告)号：EP0459222A2
公开(公告)日：1991-12-04
申请号：EP91107862.4
申请日：1991-05-15
Applicant: International Business Machines Corporation
Inventor： Vassiliadis, Stamatis , Pechanek, Gerald George
IPC: G06F15/80
Abstract: The neural computing paradigm is characterized as a dynamic and highly parallel computationally intensive system typically consisting of input weight multiplications, product summation, neural state calculations, and complete connectivity among the neurons. Herein is described neural network architecture called SNAP which uses a unique intercommunication scheme within an array structure that provides high performance for completely connected network models such as the Hopfield model. SNAP's packaging and expansion capabilities are addressed, demonstrating SNAP's scalability to larger networks.
Abstract translation: 神经计算范例的特征在于动态和高度并行的计算密集型系统，通常由输入权重乘积，乘积求和，神经状态计算以及神经元之间的完全连通性组成。 这里描述了称为SNAP的神经网络架构，其在阵列结构内使用独特的相互通信方案，为诸如Hopfield模型的完全连接的网络模型提供高性能。 SNAP的封装和扩展功能得到了解决，展示了SNAP对大型网络的可扩展性。
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公开(公告)号：EP0347557A2
公开(公告)日：1989-12-27
申请号：EP89107432.0
申请日：1989-04-25
Applicant: International Business Machines Corporation
Inventor： Pechanek, Gerald George , Shippy, David James , Snedaker, Mark Carl , Woodward, Sandra Sue
IPC: G06F13/42
CPC classification number: G06F13/4217
Abstract: A synchronous parallel data bus particularly adapted for use in a data processing system where it is necessary to transfer data over long distances. The physical connection between communicating units includes a plurality of wires adapted to carry the parallel data signal and a wire which carries a clock signal to the remote unit. When data is transmitted from the remote unit to the base unit, the clock signal which originated at the base unit and was transmitted to the remote unit is "turned around" and transmitted back to the base unit for use in receiving the data from the remote unit.
Abstract translation: 特别适用于需要长距离传输数据的数据处理系统中的同步并行数据总线。 通信单元之间的物理连接包括适于携带并行数据信号的多条线路和将远程单元携带时钟信号的线路。 当数据从远程单元发送到基本单元时，发送到基站单元并发送到远程单元的时钟信号被“转向”并被发送回到基本单元以用于从远程单元接收数据 单元。
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公开(公告)号：EP0564847A2
公开(公告)日：1993-10-13
申请号：EP93104154.5
申请日：1993-03-15
Applicant: International Business Machines Corporation
IPC: G06F15/80
CPC classification number: G06F15/8023
Abstract: Image processing for multimedia workstations is a computationally intensive task requiring special purpose hardware to meet the high speed requirements associated with the task. One type of specialized hardware that meets the computation high speed requirements is the mesh connected computer. Such a computer becomes a massively parallel machine when an array of computers interconnected by a network are replicated in a machine. The nearest neighbor mesh computer consists of an N x N square array of Processor Elements(PEs) where each PE is connected to the North, South, East and West PEs only. Assuming a single wire interface between PEs, there are a total of 2N² wires in the mesh structure. Under the assumtion of SIMD operation with uni-directional message and data transfers between the processing elements in the meah, for example all PES transferring data North, it is possible to reconfigure the array by placing the symmetric processing elements together and sharing the north-south wires with the east-west wires, thereby reducing the wiring complexity in half, i.e. N² without affecting performance. The resulting diagonal folded mesh array processor, which is called Oracle, allows the matrix transformation operation to be accomplished in one cycle by simple interchange of the data elements in the dual symmetric processor elements. The use of Oracle for a parallel 2-D convolution mechanish for image processing and multimedia applications and for a finite difference method of solving differential equations is presented, concentrating on the computational aspects of the algorithm.
Abstract translation: 多媒体工作站的图像处理是一项计算密集型任务，需要专用硬件来满足与任务相关的高速度要求。 一种满足计算高速要求的专用硬件是网状计算机。 当通过网络互连的计算机阵列在机器中复制时，这样的计算机变成大规模并行机器。 最近邻网格计算机由处理器元素（PE）的N×N个正方形阵列组成，其中每个PE仅连接到北，南，东和西PE。 假设PE之间的单线接口，网格结构中总共有2N条2线。 在SIMD操作的假设下，单向消息和数据传输在meah中的处理元素之间，例如所有PES传输数据北部，可以通过将对称处理元素放在一起并共享南北部来重新配置阵列 电线与东西电线，从而将布线复杂度降低一半，即N <2而不影响性能。 所得到的对称折叠网格阵列处理器（称为Oracle）允许通过双对称处理器元件中的数据元素的简单交换在一个周期内完成矩阵变换操作。 提出了使用Oracle进行图像处理和多媒体应用的并行2-D卷积机制，并提出了一种求解微分方程的有限差分方法，重点是算法的计算方面。
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Patent Agency Ranking
公开(公告)号：EP0328871A2
公开(公告)日：1989-08-23
申请号：EP89100516.7
申请日：1989-01-13
Applicant: International Business Machines Corporation
Inventor： Vassiliadis, Stamatis , Putrino, Michael , Huffman, Ann Elizabeth , Feal, Brice John , Pechanek, Gerald George
CPC classification number: G06F7/57 , G06F7/026 , G06F7/49905 , G06F7/505 , G06F9/30094
Abstract: The described embodiments of the present invention determine when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another emobodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.
Abstract translation: 本发明的所描述的实施例确定了两个操作数在不使用加法器的情况下直接等效于操作数。 在一个实施例中，等于零的和的条件由半和确定以携带和传送从输入操作数导出的运算符。 这些操作数用于一些已知类型的加法器，并且因此可以从并行加法器提供给条件预测电路。 在另一个实施例中，用于进位保存加法器的方程被修改以提供专门设计用于当操作数的和等于零时确定条件的电路。 该和等于零电路大大减少了门延迟和门数，从而允许中央处理单元确定两个操作数的实际总和之前的状态。 这样就可以使CPU更快地对状况作出反应，从而提高整体系统的速度。
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公开(公告)号：EP0459222A3
公开(公告)日：1994-03-30
申请号：EP91107862.4
申请日：1991-05-15
Applicant: International Business Machines Corporation
Inventor： Vassiliadis, Stamatis , Pechanek, Gerald George
IPC: G06F15/80
Abstract: The neural computing paradigm is characterized as a dynamic and highly parallel computationally intensive system typically consisting of input weight multiplications, product summation, neural state calculations, and complete connectivity among the neurons. Herein is described neural network architecture called SNAP which uses a unique intercommunication scheme within an array structure that provides high performance for completely connected network models such as the Hopfield model. SNAP's packaging and expansion capabilities are addressed, demonstrating SNAP's scalability to larger networks.
Abstract translation: 神经计算范例的特征是动态的和高度并行的计算密集系统，通常由输入权重乘法，乘积求和，神经状态计算以及神经元之间的完全连通性组成。 这里描述了称为SNAP的神经网络架构，其在阵列结构内使用独特的互通方案，为完全连接的网络模型（例如Hopfield模型）提供高性能。 SNAP的打包和扩展功能已得到解决，从而证明了SNAP对大型网络的可扩展性。
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公开(公告)号：EP0328871A3
公开(公告)日：1991-07-03
申请号：EP89100516.7
申请日：1989-01-13
Applicant: International Business Machines Corporation
Inventor： Vassiliadis, Stamatis , Putrino, Michael , Huffman, Ann Elizabeth , Feal, Brice John , Pechanek, Gerald George
CPC classification number: G06F7/57 , G06F7/026 , G06F7/49905 , G06F7/505 , G06F9/30094
Abstract: The described embodiments of the present invention determine when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another emobodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.
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公开(公告)号：EP0347557A3
公开(公告)日：1991-06-05
申请号：EP89107432.0
申请日：1989-04-25
Applicant: International Business Machines Corporation
Inventor： Pechanek, Gerald George , Shippy, David James , Snedaker, Mark Carl , Woodward, Sandra Sue
IPC: G06F13/42
CPC classification number: G06F13/4217
Abstract: A synchronous parallel data bus particularly adapted for use in a data processing system where it is necessary to transfer data over long distances. The physical connection between communicating units includes a plurality of wires adapted to carry the parallel data signal and a wire which carries a clock signal to the remote unit. When data is transmitted from the remote unit to the base unit, the clock signal which originated at the base unit and was transmitted to the remote unit is "turned around" and transmitted back to the base unit for use in receiving the data from the remote unit.
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公开(公告)号：EP0348672A2
公开(公告)日：1990-01-03
申请号：EP89109518.4
申请日：1989-05-26
Applicant: International Business Machines Corporation
Inventor： Pechanek, Gerald George , Shippy, David James , Snedaker, Mark Carl , Woodward, Sandra Sue
CPC classification number: G06F13/36
Abstract: An input/output bus for a data processing system which has extended addressing capabilities and a variable length handshake which accommodates the difference delays associated with various sets of logic and a two part address field which allows a bus unit and channel to be identified. The various units can disconnect from the bus during internal processing to free the bus for other activity. The unit removes the busy signal prior to dropping the data lines to allow a bus arbitration sequence to occur without slowing down the bus.
Abstract translation: 一种用于数据处理系统的输入/输出总线，其具有扩展的寻址能力和可变长度握手，其适应与各种逻辑集合相关联的差分延迟以及允许识别总线单元和通道的两部分地址字段。 在内部处理过程中，各种设备可以与总线断开连接，以免公共汽车进行其他活动。 在丢弃数据线之前，该单元去除忙信号，以允许总线仲裁序列发生而不会使总线减速。
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