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公开(公告)号：EP0063228B1
公开(公告)日：1985-09-11
申请号：EP82101679.7
申请日：1982-03-04
IPC分类号： H03F3/45
CPC分类号： H03F3/45089 , H03F3/42 , H03F2203/45301 , H03F2203/45318 , H03F2203/45702
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2.发明公开A method and apparatus for producing a DC balanced (0,4) run length limited rate 8B/10B code from an input data stream 失效用于生成来自输入数据流的直流平衡（0,4）运行长度有限速率8B / 10B代码的方法和装置
公开(公告)号：EP0097763A3
公开(公告)日：1987-01-14
申请号：EP83101758
申请日：1983-02-23
CPC分类号： H03M5/145 , H04L25/4908
摘要： A binary DC balanced code and an encoder circuit for producing such code is described, which translates an 8 bit byte of information into 10 binary digits for transmission over electromagnetic or optical transmission lines subject to timing and low frequency constraints. The significance of this code is that it combines a low circuit count for implementation with excellent performance near the theoretical limits, when measured with the commonly accepted criteria. The 8B/10B coder (12,14,16,18) is partitioned into a 5B/6B (12) and 3B/4B (14) coder. The input code points are assigned to the output code points so the number of bit changes required for translation is minimized and can be grouped into a few classes.
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3.发明公开A method and apparatus for producing a DC balanced (0,4) run length limited rate 8B/10B code from an input data stream 失效用于从输入数据流中产生的比8B / 10B无DC（0,4） - 运行长度有限码的方法和装置。
公开(公告)号：EP0097763A2
公开(公告)日：1984-01-11
申请号：EP83101758.7
申请日：1983-02-23
CPC分类号： H03M5/145 , H04L25/4908
摘要： A binary DC balanced code and an encoder circuit for producing such code is described, which translates an 8 bit byte of information into 10 binary digits for transmission over electromagnetic or optical transmission lines subject to timing and low frequency constraints. The significance of this code is that it combines a low circuit count for implementation with excellent performance near the theoretical limits, when measured with the commonly accepted criteria. The 8B/10B coder (12,14,16,18) is partitioned into a 5B/6B (12) and 3B/4B (14) coder. The input code points are assigned to the output code points so the number of bit changes required for translation is minimized and can be grouped into a few classes.
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4.发明授权A method and apparatus for producing a DC balanced (0,4) run length limited rate 8B/10B code from an input data stream 失效用于生成来自输入数据流的直流平衡（0,4）运行长度有限速率8B / 10B代码的方法和装置
公开(公告)号：EP0097763B1
公开(公告)日：1988-09-21
申请号：EP83101758.7
申请日：1983-02-23
CPC分类号： H03M5/145 , H04L25/4908
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公开(公告)号：EP0063228A1
公开(公告)日：1982-10-27
申请号：EP82101679.7
申请日：1982-03-04
IPC分类号： H03F3/45
CPC分类号： H03F3/45089 , H03F3/42 , H03F2203/45301 , H03F2203/45318 , H03F2203/45702
摘要： Each cascaded amplifier stage comprises two input transistors (118, 120) and two control transistors (110, 112) respectively supplied with bias voltage V and bias current I. The differential current flowing through transistors (118,120) is amplified by each stage. By connecting diode loads, (D1 D2); (D3, D4) and (D5, D6) in the connections between the emitters of transistors (118', 120') and the base collector connections of transistors (110'/112') and (120'/110) etc., the amplification in each stage is increased so that the differential current is amplified at a higher rate than the proportion of 12:11; 13:12 etc.
摘要翻译： 每个级联放大器级包括分别被提供有偏置电压V和偏置电流I的两个输入晶体管（118,120）和两个控制晶体管（110,112）。流过晶体管（118,120）的差分电流被每个级放大。 通过连接二极管负载（D1 D2）; 晶体管发射极（118分钟，120分钟）和晶体管的基极集电极连接（110分钟/ 112分钟）和（120分钟/ 110）等之间的连接中的（D3，D4）和（D5，D6） 增加每个阶段的放大，使得差分电流以比I2：I1的比例更高的速率被放大; I3：I2等
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