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    RF POWER AMPLIFIERS WITH IMPROVED EFFICIENCY AND OUTPUT POWER
    1.
    发明公开
    RF POWER AMPLIFIERS WITH IMPROVED EFFICIENCY AND OUTPUT POWER 审中-公开
    以更高的效率和功率输出的射频功率放大器

    公开(公告)号：EP2700160A1

    公开(公告)日：2014-02-26

    申请号：EP12717555.2

    申请日：2012-04-19

    申请人： Qualcomm Incorporated

    发明人： PRESTI, Calogero, D.

    IPC分类号： H03F3/24 ,  H03F1/22 ,  H03F3/193 ,  H03F3/195 ,  H03F1/52 ,  H03F3/45

    CPC分类号： H03F3/245 ,  H03F1/223 ,  H03F1/523 ,  H03F3/193 ,  H03F3/195 ,  H03F3/45179 ,  H03F2203/45296 ,  H03F2203/45301 ,  H03F2203/45311 ,  H03F2203/45731

    摘要： A Doherty amplifier (10) is operable to receive an input signal (Pin) and to provide an amplified output signal (Pout) at an amplifier output (95). The Doherty amplifier (10) comprises: first (30) and second (40) amplifier stages, each amplifier stage being switchable between an amplifying and a non -amplifying state, each amplifier stage being arranged in parallel to receive the input signal (Pin) and, in the amplifying state, to provide a respective amplified signal at a respective amplifier stage output; and an output network (50) comprising first (80) and second (90) impedance transformers, each impedance transformer being coupled at a first side with a respective amplifier stage output and being coupled together in parallel at a second side with the amplifier output (95). By using an alternative, parallel architecture, the impedance transformation ratio experienced by an amplified signal under different operating conditions is significantly reduced compared to that of a traditional architecture which uses a single, series, impedance transformer which combines and transforms the amplified signals from both amplifier stages (30, 40).

    Linear voltage regulator utilizing a large range of bypass-capacitance
    2.
    发明公开
    Linear voltage regulator utilizing a large range of bypass-capacitance 审中-公开
    Lineere Spannungsregler mit einemgroßenBereich von Bypass-Kapazität

    公开(公告)号：EP2952995A1

    公开(公告)日：2015-12-09

    申请号：EP14171088.9

    申请日：2014-06-04

    申请人： Dialog Semiconductor (UK) Limited

    发明人： Drebinger, Stephan ,  Curra, Roberto

    IPC分类号： G05F1/575 ,  H03F3/34

    CPC分类号： G05F1/575 ,  H03F3/34 ,  H03F3/45183 ,  H03F2200/297 ,  H03F2203/45301 ,  H03F2203/45674

    摘要： The present document relates to amplifiers, notably multi-stage amplifiers, such as linear regulators or linear voltage regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients. An amplifier (300) is described. The amplifier (300) comprises a first amplification stage (302) configured to provide an intermediate voltage, based on an outer feedback voltage (107) and based on a reference voltage (108). Furthermore, the amplifier (300) comprises an output stage (301) configured to provide a load current at an output voltage (305) based on the intermediate voltage (528). In addition, the amplifier (300) comprises an outer feedback circuit (104) configured to derive the outer feedback voltage (107) from the output voltage (305). The output stage (301) comprises a buffer (301) configured to provide a drive voltage based on the intermediate voltage (528) and based on an inner feedback voltage derived from the output voltage (305). The buffer (301) comprises a pass device (201) which is configured to provide the load current (527) at the output voltage (305) based on the drive voltage.

    摘要翻译： 本文件涉及放大器，特别是多级放大器，例如线性稳压器或线性稳压器（例如低压差稳压器），其被配置为提供经受负载瞬变的恒定输出电压。 描述放大器（300）。 放大器（300）包括第一放大级（302），其被配置为基于外部反馈电压（107）和基于参考电压（108）提供中间电压。 此外，放大器（300）包括被配置为基于中间电压（528）在输出电压（305）提供负载电流的输出级（301）。 此外，放大器（300）包括被配置为从输出电压（305）导出外部反馈电压（107）的外部反馈电路（104）。 输出级（301）包括缓冲器（301），其被配置为基于中间电压（528）提供驱动电压并且基于从输出电压（305）导出的内部反馈电压。 缓冲器（301）包括通过装置（201），其被配置为基于驱动电压提供输出电压（305）处的负载电流（527）。

    Differential amplifier
    4.
    发明公开
    Differential amplifier 失效
    Differenzverstärker。

    公开(公告)号：EP0063228A1

    公开(公告)日：1982-10-27

    申请号：EP82101679.7

    申请日：1982-03-04

    申请人： International Business Machines Corporation

    发明人： Rogers, Dennis Lee ,  Widmer, Albert Xavier

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45089 ,  H03F3/42 ,  H03F2203/45301 ,  H03F2203/45318 ,  H03F2203/45702

    摘要： Each cascaded amplifier stage comprises two input transistors (118, 120) and two control transistors (110, 112) respectively supplied with bias voltage V and bias current I. The differential current flowing through transistors (118,120) is amplified by each stage. By connecting diode loads, (D1 D2); (D3, D4) and (D5, D6) in the connections between the emitters of transistors (118', 120') and the base collector connections of transistors (110'/112') and (120'/110) etc., the amplification in each stage is increased so that the differential current is amplified at a higher rate than the proportion of 12:11; 13:12 etc.

    摘要翻译： 每个级联放大器级包括分别被提供有偏置电压V和偏置电流I的两个输入晶体管（118,120）和两个控制晶体管（110,112）。流过晶体管（118,120）的差分电流被每个级放大。 通过连接二极管负载（D1 D2）; 晶体管发射极（118分钟，120分钟）和晶体管的基极集电极连接（110分钟/ 112分钟）和（120分钟/ 110）等之间的连接中的（D3，D4）和（D5，D6） 增加每个阶段的放大，使得差分电流以比I2：I1的比例更高的速率被放大; I3：I2等

    CLOCK AND DATA DRIVERS WITH ENHANCED TRANSCONDUCTANCE AND SUPPRESSED OUTPUT COMMON-MODE
    5.
    发明公开
    CLOCK AND DATA DRIVERS WITH ENHANCED TRANSCONDUCTANCE AND SUPPRESSED OUTPUT COMMON-MODE 审中-公开
    TAKT- UND DATENTREIBER MITERHÖHTERTRANSKONDUKTANZ UNDUNTERDRÜCKTEMGLEICHTAKTBEREICH

    公开(公告)号：EP3066756A1

    公开(公告)日：2016-09-14

    申请号：EP14859633.1

    申请日：2014-11-05

    申请人： Qualcomm Incorporated

    发明人： SU, Wenjun ,  YIN, Guangming ,  ZHU, Quanqing

    IPC分类号： H03K5/12

    CPC分类号： H03F3/45762 ,  H03F1/0277 ,  H03F3/211 ,  H03F3/45183 ,  H03F3/45609 ,  H03F3/72 ,  H03F2200/555 ,  H03F2200/72 ,  H03F2203/45288 ,  H03F2203/45301 ,  H03F2203/45511 ,  H03F2203/45638 ,  H03F2203/45644 ,  H03F2203/45702 ,  H03K5/12

    摘要： Methods, apparatus, and means for maintaining a low output common-mode voltage in a driver are provided. One example apparatus includes a first differential amplifier stage configured to provide a differential output for the apparatus; and a second differential amplifier stage configured to drive the first differential amplifier stage, the second differential amplifier stage including a pair of pre-driver amplifiers, a pair of n-stage circuits, and an input skew averaging circuit, wherein each of the pair of n-stage units is split into two half blocks. The input skew averaging circuit is configured to suppress the output common-mode voltage by driving the blocks with complementary digital inputs to average out a skew in a gate-to-source voltage of the pair of n-stage circuits. For certain aspects, two feed-forward capacitors may be added to enhance the transconductance and operating speed of main transistors of the first differential amplifier stage.

    摘要翻译： 提供了用于在驱动器中维持低输出共模电压的方法，装置和装置。 一个示例性设备包括：第一差分放大器级，被配置为提供用于该设备的差分输出; 以及第二差分放大器级，被配置为驱动所述第一差分放大器级，所述第二差分放大器级包括一对预驱动放大器，一对n级电路和输入偏斜平均电路，其中， n级单元分为两个半块。 输入偏斜平均电路被配置为通过用互补数字输入驱动块来抑制输出共模电压，以平均一对n级电路的栅极 - 源极电压的偏斜。 对于某些方面，可以添加两个前馈电容器以增强第一差分放大器级的主晶体管的跨导和操作速度。

    HYBRID AMPLIFIER
    6.
    发明公开
    HYBRID AMPLIFIER 审中-公开
    HYBRIDVERSTÄRKER

    公开(公告)号：EP2944026A1

    公开(公告)日：2015-11-18

    申请号：EP14702373.3

    申请日：2014-01-10

    申请人： Qualcomm Incorporated

    发明人： RAJAEE, Omid

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45188 ,  H03F2203/45301 ,  H03F2203/45311 ,  H03F2203/45371 ,  H03F2203/45661

    摘要： Exemplary embodiments are directed to systems, devices, and methods for enhancing a telescopic amplifier. An amplifier may include a differential pair of input transistors including at least one transistor configured to receive a first input and at least one other transistor configured to receive a second input. The amplifier may further include a cascode circuit including a first pair of transistors coupled to the at least one transistor of the differential pair to form a first plurality of current paths configured to generate a first output. The cascode circuit maymo also include a second pair of transistors coupled to the at least one other transistor of the differential pair to form a second plurality of currents paths configured to generate a second output.

    DRIVER CIRCUIT
    9.
    发明公开
    DRIVER CIRCUIT 审中-公开
    驱动电路

    公开(公告)号：EP3161913A1

    公开(公告)日：2017-05-03

    申请号：EP15734546.3

    申请日：2015-06-26

    申请人： Finisar Corporation

    发明人： ZAFRANY, Arik ,  KALOGERAKIS, Georgios

    IPC分类号： H01S5/042 ,  H03F3/45 ,  H04B10/50

    CPC分类号： H03K17/6871 ,  H01S5/042 ,  H01S5/0427 ,  H03F3/45085 ,  H03F3/45179 ,  H03F3/45282 ,  H03F2203/45288 ,  H03F2203/45301 ,  H03F2203/45554 ,  H03F2203/45562 ,  H03F2203/45598 ,  H03F2203/45702 ,  H04B10/502 ,  H04B10/503

    摘要： A circuit may include first and second input nodes, first and second output nodes, first and second intermediate nodes, first and second resistances, a first amplification transistor coupled to the first input node, the first resistance, and the first intermediate node and a second amplification transistor coupled to the second input node, the second resistance, and the second intermediate node. The circuit may also include a first active device coupled to the first output node and the first intermediate node, a second active device coupled to the second output node and the second intermediate node, a first output transistor coupled to the first output node and configured to conduct based on a second intermediate signal on the second intermediate node, and a second output transistor coupled to the second output node and configured to conduct based on a first intermediate signal on the first intermediate node.

    摘要翻译： 电路可以包括第一和第二输入节点，第一和第二输出节点，第一和第二中间节点，第一和第二电阻，耦合到第一输入节点的第一放大晶体管，第一电阻和第一中间节点以及第二 放大晶体管，耦合到第二输入节点，第二电阻和第二中间节点。 该电路还可以包括耦合到第一输出节点和第一中间节点的第一有源器件，耦合到第二输出节点和第二中间节点的第二有源器件，耦合到第一输出节点的第一输出晶体管， 基于第二中间节点上的第二中间信号进行导通;以及第二输出晶体管，耦合到第二输出节点并且被配置为基于第一中间节点上的第一中间信号进行导通。