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    Interlaced programmable logic array having shared elements
    2.
    发明公开
    Interlaced programmable logic array having shared elements 失效
    具有共享元素的可互操作的可编程逻辑阵列

    公开(公告)号：EP0096225A3

    公开(公告)日：1985-03-20

    申请号：EP83104486

    申请日：1983-05-06

    申请人： International Business Machines Corporation

    发明人： Kalter, Howard Leo ,  Wiedman, Francis Walter

    IPC分类号： H03K19/177 ,  G06F07/50

    CPC分类号： G06F7/5057 ,  H03K19/096 ,  H03K19/1772

    摘要： A programmable PLA circuit in which an interlaced AND/OR array (30, 32, 34) is provided which has both common input (16) and common output lines (36). Separate AND and OR functions are generated during two different timing intervals (D1, D2) such that both of the logical arrays can physically share input and output circuit elements. A binary adder is described in which pairs of array output lines are applied to the same Exclusive-NOR circuits (40) during the two time intervals to provide the Exclusive-NOR of product terms during the AND array time interval (D1) and to provide the Exclusive-NOR of sums of product terms or the sum of the Exclusive-NOR of product terms during the second time interval (D2).

    Interlaced programmable logic array having shared elements
    3.
    发明公开
    Interlaced programmable logic array having shared elements 失效
    蜿蜒与共享元素的可编程逻辑阵列。

    公开(公告)号：EP0096225A2

    公开(公告)日：1983-12-21

    申请号：EP83104486.2

    申请日：1983-05-06

    申请人： International Business Machines Corporation

    发明人： Kalter, Howard Leo ,  Wiedman, Francis Walter

    IPC分类号： H03K19/177 ,  G06F7/50

    CPC分类号： G06F7/5057 ,  H03K19/096 ,  H03K19/1772

    摘要： A programmable PLA circuit in which an interlaced AND/OR array (30, 32, 34) is provided which has both common input (16) and common output lines (36). Separate AND and OR functions are generated during two different timing intervals (D1, D2) such that both of the logical arrays can physically share input and output circuit elements. A binary adder is described in which pairs of array output lines are applied to the same Exclusive-NOR circuits (40) during the two time intervals to provide the Exclusive-NOR of product terms during the AND array time interval (D1) and to provide the Exclusive-NOR of sums of product terms or the sum of the Exclusive-NOR of product terms during the second time interval (D2).