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1.发明公开Schottky barrier diode and method of making it 失效肖特基Sperrschichtdiode和Verfahren zu deren Herstellung。
公开(公告)号：EP0032195A1
公开(公告)日：1981-07-22
申请号：EP80107627.4
申请日：1980-12-04
IPC分类号： H01L29/48 , H01L21/316 , H01L21/28
CPC分类号： H01L29/66848 , H01L21/74 , H01L29/47 , H01L29/872 , Y10S148/131 , Y10S148/139 , Y10S148/141
摘要： The anode (40) and cathode contact (32) of the diode are contiguously located on a semiconductor surface and separated by an insulating coating (36) on cathode contact (32). Preferably the anode (40) consists of two regions (40) separated by coated cathode contact (32) and laterally surrounded by recessed oxide area (16).
The method of making includes the steps of forming cathode contact (32) of a layer of conductive material and applying insulative coating (36) onto it where after this step at least one area of the semiconductor surface adjoining coated cathode contact (32) is exposed, of blanket depositing a metal layer and causing the reaction of the metal with the semiconductor material to produce anode (40) that is self-aligned with respect to cathode contact (32).
The diode may be incorporated into merged transistor logic devices in large scale integration applications.摘要翻译： 二极管的阳极（40）和阴极（32）连接地位于半导体表面上并由阴极接触件（32）上的绝缘涂层（36）分开。 优选地，阳极（40）由被涂覆的阴极接触（32）分开并被凹陷的氧化物区域（16）侧向包围的两个区域（40）组成。 ...制造方法包括以下步骤：形成导电材料层的阴极接触（32）并在其上施加绝缘涂层（36），其中在该步骤之后，半导体表面的至少一个区域邻接涂覆的阴极接触 （32）暴露，覆盖沉积金属层并使金属与半导体材料的反应产生相对于阴极接触（32）自对准的阳极（40）。 在大规模集成应用中，二极管可并入到合并的晶体管逻辑器件中。
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公开(公告)号：EP0069853A3
公开(公告)日：1984-05-16
申请号：EP82104710
申请日：1982-05-28
IPC分类号： H03K19/013 , H03K19/088
CPC分类号： H03K19/088 , H03K19/001 , H03K19/013
摘要： A Transistor-Transistor Logic (TTL) gate circuit is disclosed comprising an input transistor T1, an inverter transistor T2, an output transistor T3 and a pull-up transistor T4. When T2, T3 are non-conducting, VB appears at the output 12 and when T2, T3 are conducting, the output is substantially at earth. To achieve fast switching of T3 a different smaller amount of base current is applied to the inverter transistor T2 than is applied to the base of the output transistor T3. As shown, a current mirror circuit (T5, T6) can be used to control the amount of base current flowing between the input transistor (T1) collector terminal and the base terminal of the inverter transistor (T2). The mirror circuits limit the base current of T2 to an amount less than the base current that flows between the input transistor collector terminal and the base terminal of the output transistor T3. The value of R3 also limits the current though T2. In another embodiment, a resistor in series with the base of the inverter transistor performs the same function as the current mirror circuit.
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公开(公告)号：EP0021400A1
公开(公告)日：1981-01-07
申请号：EP80103550.2
申请日：1980-06-24
CPC分类号： H01L23/5226 , H01L21/76889 , H01L23/53271 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a single crystal semiconductor material (14) having an N conductivity type region (10) and a P conductivity type region (12) which are electrically interconnected by a layer (18) of said semiconductor material in polycrystalline form doped to make an electrical contact with the N type region (10), a layer (20) of a combination of said semiconductor material and a refractory metal and a layer (24) of said semiconductor material in polycrystalline form doped to form an electrical contact with the P type region (12).
摘要翻译： 半导体器件包括具有N导电类型区域（10）和P导电类型区域（12）的单晶半导体材料（14），所述导电型区域（12）通过掺杂多晶形式的所述半导体材料的层（18）电连接， 与N型区域（10）的电接触，所述半导体材料和难熔金属的组合的层（20）和所述半导体材料的层（24）以多晶形式被掺杂以与P形成电接触 类型区域（12）。
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4.发明公开
公开(公告)号：EP0045848A1
公开(公告)日：1982-02-17
申请号：EP81105228.1
申请日：1981-07-06
发明人： Reisman, Arnold , Silvestri, Victor Joseph , Tang, Denny Duan-Lee , Wiedmann, Siegfried Kurt , Yu, Hwa Nien
CPC分类号： H01L21/76248 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/743 , H01L27/0821 , H01L29/42304
摘要： In a planar semiconductor integrated circuit, a buried isolating layer (9) confines equal area PN junctions of a vertical bipolar transistor (3) and a lateral bipolar transistor (5) to the intrinsic regions of the transistors. This avoids the formation of parasitic PN junctions and so leads to improved performance when the transistors are operated in saturation as in TTL circuits. A method of making such an integrated circuit involves the simultaneous deposition of polycrystalline semiconductor on the isolating layer and monocrystalline semiconductor onto the substrate through holes in the isolating layer. Alternatively, a thin nucleating film may be first deposited on the isolating layer so that monocrystalline semiconductor can be deposited on the isolating layer as well as on the substrate.
摘要翻译： 在平面的半导体集成电路，掩埋隔离层（9）地限制垂直双极晶体管（3）和横向双极性晶体管（5）连接到晶体管的本征区域的面积相等的PN结。 这避免了寄生PN结的形成，并因此导致改善的性能当晶体管在饱和操作为在TTL电路。 使上集成电路调查的方法包括隔离层和单晶半导体到基板上的多晶半导体的通过在隔离层孔中的同时沉积。 可替代地，薄膜成核可以首先沉积在隔离层上，从而确实单晶半导体可在隔离层上，以及在衬底上沉积。
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公开(公告)号：EP0021403A1
公开(公告)日：1981-01-07
申请号：EP80103559.3
申请日：1980-06-24
发明人： Feth, George Clarence , Ning, Tak Hung , Tang, Denny Duan-Lee , Wiedmann, Siegfried Kurt , Yu, Hwa Nien
IPC分类号： H01L27/02 , H01L21/60 , H01L21/285 , H01L21/82
CPC分类号： H01L21/76897 , H01L21/28525 , H01L27/0233
摘要： Self-aligned semiconductor circuits and process for manufacturing the circuits in which a plurality of transistors (206, 208, 240; 206, 208, 242) is provided, the collector regions/contacts (240,228; 242, 228) and the base regions/contacts (254, 252; 256, 252) being mutually self-aligned. In one embodiment, the collectors have conductive layer contacts (such as metal) and are self-aligned to polysilicon base contacts while in another embodiment the base contacts are comprised of a conductive (metal) layer while polysilicon is used for the collector contacts. The collectors (240, 242) of these transistors can be butted to a recessed field oxide (214) to reduce the extrinsic base area and to minimize excess charge storage in the base region (208). The base contacts, whether polysilicon or metal, etc., provide alternate base current paths so that the removal of the extrinsic base area does not adversely affect the total amount of base current which can flow.
摘要翻译： 自对准半导体电路和制造其中提供多个晶体管（206,208,240; 206,208,242）的电路的工艺，集电极区域/触点（240,228; 242,228）和基极 区域/触点（254,252; 256,252）相互自对准。 在一个实施例中，集电器具有导电层接触（例如金属）并且与多晶硅基底触点自对准，而在另一实施例中，基极触点由导电（金属）层组成，而多晶硅用于集电极触点。 这些晶体管的集电极（240,242）可以对接到凹陷的场氧化物（214），以减少非本征基极面积并且使基极区域（208）中的过剩电荷存储最小化。 基极触点（无论多晶硅或金属等）是否提供可选的基极电流路径，以便去除非本征基极面积不会不利地影响可流过的基极电流的总量。
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公开(公告)号：EP0021141B1
公开(公告)日：1983-04-06
申请号：EP80103078.4
申请日：1980-06-03
IPC分类号： H03K19/013 , H03K19/082 , H03K17/66 , H03K17/74
CPC分类号： H03K17/667 , H03K19/013 , H03K19/082
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公开(公告)号：EP0069853A2
公开(公告)日：1983-01-19
申请号：EP82104710.7
申请日：1982-05-28
IPC分类号： H03K19/013 , H03K19/088
CPC分类号： H03K19/088 , H03K19/001 , H03K19/013
摘要： A Transistor-Transistor Logic (TTL) gate circuit is disclosed comprising an input transistor T1, an inverter transistor T2, an output transistor T3 and a pull-up transistor T4. When T2, T3 are non-conducting, VB appears at the output 12 and when T2, T3 are conducting, the output is substantially at earth. To achieve fast switching of T3 a different smaller amount of base current is applied to the inverter transistor T2 than is applied to the base of the output transistor T3. As shown, a current mirror circuit (T5, T6) can be used to control the amount of base current flowing between the input transistor (T1) collector terminal and the base terminal of the inverter transistor (T2). The mirror circuits limit the base current of T2 to an amount less than the base current that flows between the input transistor collector terminal and the base terminal of the output transistor T3. The value of R3 also limits the current though T2. In another embodiment, a resistor in series with the base of the inverter transistor performs the same function as the current mirror circuit.
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8.发明公开Bipolar inverter and its use in a logic circuit 失效Bipolarer逆变器和seine Verwendung在einer logischen Schaltung。
公开(公告)号：EP0021141A1
公开(公告)日：1981-01-07
申请号：EP80103078.4
申请日：1980-06-03
IPC分类号： H03K19/013 , H03K19/082 , H03K17/66 , H03K17/74
CPC分类号： H03K17/667 , H03K19/013 , H03K19/082
摘要： Bipolar logic circuits such as inverters and NAND circuits are disclosed which are of extremely low DC power dissipation and very high speed. The basic circuit is an inverter circuit which incorporates at least a single switchable transistor (3). The emitter (6) of the NPN transistor (3) is connected to a potential level which may be ground while the collector is connected via a load device, a resistor or a complementary PNP transistor (2), to a positive power supply potential. The base (8) of the NPN transistor (3) is connected to a source (10) of standby current and via a parallel combination of a capacitor (14) and diode (12) to an input terminal (15). When the NPN transistor (3) is switched OFF by the application of a negatively going signal, standby current from the current source (10) is switched to ground via the diode (12) which has a lower switching point than the emitter-base diode of the NPN transistor. The capacitor (14) in parallel with the diode, is charged during this period so that when a positive going transient is applied at the input, the diode is backward-biased and the transient is applied along with the standby current to the base (8) of the NPN transistor, switching it to the conducting or ON state.
In addition to the basic logic circuit, a two-input NAND circuit which includes a pair of PNP bipolar transistors and a pair of NPN bipolar transistors disclosed.摘要翻译： 公开了诸如逆变器和NAND电路的双极性逻辑电路，其具有极低的DC功率消耗和非常高的速度。 基本电路是至少包含一个可切换晶体管（3）的逆变器电路。 NPN晶体管（3）的发射极（6）连接到可以被接地的电位电平，同时集电极经由负载装置，电阻器或互补PNP晶体管（2）连接到正电源电位。 NPN晶体管（3）的基极（8）通过电容器（14）和二极管（12）的并联组合连接到待机电流源（10）到输入端子（15）。 当通过施加负向信号将NPN晶体管（3）切换到OFF时，来自电流源（10）的待机电流通过具有比发射极 - 基极二极管的开关点低的二极管（12）切换到地 的NPN晶体管。 与二极管并联的电容器（14）在此期间被充电，使得当在输入端施加正向瞬态时，二极管被反向偏置，并且瞬态随着待机电流施加到基极（8 ），将其切换到导通或导通状态。 除了基本逻辑电路之外，还公开了包括一对PNP双极晶体管和一对NPN双极晶体管的双输入NAND电路。
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9.发明公开
公开(公告)号：EP0469247A3
公开(公告)日：1993-03-17
申请号：EP91107212.2
申请日：1991-05-03
IPC分类号： G11C7/00
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1051
摘要： This invention relates generally to the accessing of random access access memory arrays and, more specifically to circuits and techniques for increasing the data valid time of such memory arrays without increasing either the access or cycle times of the array. This is accomplished by providing, during a read cycle, a read signal directly to an output driver (32) and simultaneously providing, via a parallel path, a latch output to the same driver (32). The latch output is provided under control of the read signal and a returning portion of a clock pulse such that the latch output overlaps the direct read signal from a sense/read amplifier (31). An output is provided from the latch (33) until it is reset and may last well into the next read cycle even when a new read signal is present. The technique utilized, in addition to providing a longer data valid time, eliminates a response of the latch (33) to spurious read signals because a latch output is not provided until the clock is deactivated and such spurious read signals are not present during the returning portion of the clock cycle. The approach utilized also has the advantage that delays associated with prior art serially disposed latches (33) are eliminated.
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10.发明公开Circuit for increasing data-valid time which incorporates a parallel latch 失效Schaltung zurVerlängerungeinerPulslänge，die eine parallele Verriegelungsschaltungenthält。
公开(公告)号：EP0469247A2
公开(公告)日：1992-02-05
申请号：EP91107212.2
申请日：1991-05-03
IPC分类号： G11C7/00
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1051
摘要： This invention relates generally to the accessing of random access access memory arrays and, more specifically to circuits and techniques for increasing the data valid time of such memory arrays without increasing either the access or cycle times of the array. This is accomplished by providing, during a read cycle, a read signal directly to an output driver (32) and simultaneously providing, via a parallel path, a latch output to the same driver (32). The latch output is provided under control of the read signal and a returning portion of a clock pulse such that the latch output overlaps the direct read signal from a sense/read amplifier (31). An output is provided from the latch (33) until it is reset and may last well into the next read cycle even when a new read signal is present. The technique utilized, in addition to providing a longer data valid time, eliminates a response of the latch (33) to spurious read signals because a latch output is not provided until the clock is deactivated and such spurious read signals are not present during the returning portion of the clock cycle. The approach utilized also has the advantage that delays associated with prior art serially disposed latches (33) are eliminated.
摘要翻译： 本发明一般涉及随机存取存取存储器阵列的访问，更具体地涉及用于增加这种存储器阵列的数据有效时间而不增加阵列的访问或周期时间的电路和技术。 这是通过在读周期期间将读信号直接提供给输出驱动器（32）并且经由并行路径同时向同一驱动器（32）提供锁存器输出来实现的。 锁存器输出在读信号的控制下和时钟脉冲的返回部分被提供，使得锁存输出与来自读/读放大器（31）的直接读信号重叠。 从锁存器（33）提供输出，直到其被复位，并且即使存在新的读取信号，也可以持续很好地进入下一个读取周期。 除了提供更长的数据有效时间之外，所采用的技术消除了锁存器（33）对寄生读取信号的响应，因为在时钟被去激活之前不提供锁存器输出，并且在返回期间不存在这样的寄生读取信号 部分时钟周期。 所使用的方法还具有以下优点：消除了与现有技术的串联设置的锁存器（33）相关联的延迟。
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