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17 条记录 (耗时 0.01 秒)

    A bistable ballistic space charge semiconductor device
    1.
    发明公开
    A bistable ballistic space charge semiconductor device 失效
    Halbleiteranordnung mit bistabiler ballistischer Raumladungszone。

    公开(公告)号：EP0166343A2

    公开(公告)日：1986-01-02

    申请号：EP85107443.5

    申请日：1985-06-19

    申请人： International Business Machines Corporation

    发明人： Solomon, Paul Michael

    IPC分类号： H01L29/36 ,  H01L29/90

    CPC分类号： H01L29/8618 ,  H01L29/365 ,  H01L29/861

    摘要： The device comprises a low conductivity near intrinsic region (3) sandwiched between a heavily doped carrier injection region (1) and a heavily doped output region (5). The carrier injection region (1) has a wider band gap than the near intrinsic region (3), which contains a doped planar barrier (6) adjacent and parallel to the interface (2).
    The device has charge characteristics at the ballistic launcher interface that are different at different times and which give rise to different stabilities. The device has a 10 -12 second switching time.

    摘要翻译： 该器件包括夹在重掺杂载流子注入区域（1）和重掺杂输出区域（5）之间的本征区域（3）附近的低导电性。 载流子注入区域（1）具有比接近本征区域（3）更宽的带隙，其包含与界面（2）相邻并平行的掺杂平面势垒（6）。 该装置在弹道发射器接口处具有在不同时间不同并且产生不同稳定性的电荷特性。 该器件具有10 < - > 1 <2>次切换时间。

    A TTL logic gate
    2.
    发明公开
    A TTL logic gate 失效
    TTL逻辑门。

    公开(公告)号：EP0069853A2

    公开(公告)日：1983-01-19

    申请号：EP82104710.7

    申请日：1982-05-28

    申请人： International Business Machines Corporation

    发明人： Solomon, Paul Michael ,  Wiedmann, Siegfried Kurt

    IPC分类号： H03K19/013 ,  H03K19/088

    CPC分类号： H03K19/088 ,  H03K19/001 ,  H03K19/013

    摘要： A Transistor-Transistor Logic (TTL) gate circuit is disclosed comprising an input transistor T1, an inverter transistor T2, an output transistor T3 and a pull-up transistor T4. When T2, T3 are non-conducting, VB appears at the output 12 and when T2, T3 are conducting, the output is substantially at earth. To achieve fast switching of T3 a different smaller amount of base current is applied to the inverter transistor T2 than is applied to the base of the output transistor T3. As shown, a current mirror circuit (T5, T6) can be used to control the amount of base current flowing between the input transistor (T1) collector terminal and the base terminal of the inverter transistor (T2). The mirror circuits limit the base current of T2 to an amount less than the base current that flows between the input transistor collector terminal and the base terminal of the output transistor T3. The value of R3 also limits the current though T2. In another embodiment, a resistor in series with the base of the inverter transistor performs the same function as the current mirror circuit.

    Staggered bandgap gate field effect transistor
    7.
    发明公开
    Staggered bandgap gate field effect transistor 失效
    STAGGERED BANDGAP GATE场效应晶体管

    公开(公告)号：EP0275540A3

    公开(公告)日：1989-11-08

    申请号：EP87119140.9

    申请日：1987-12-23

    申请人： International Business Machines Corporation

    发明人： Solomon, Paul Michael

    IPC分类号： H01L29/64 ,  H01L29/80 ,  H01L29/205

    CPC分类号： H01L29/205 ,  H01L29/432 ,  H01L29/778

    摘要： A field effect transistor having a highly doped gate wherein both the gate and the channel are different semiconductors with an energy band relationship that provides a barrier to both electrons and holes. The energy band relationship is staggered so that tunneling of electrons from the channel into the gate and holes from the gate into the channel is suppressed. An example structure is an InP light p conductivity type channel material (2) with a heavily doped AlInAs p⁺⁺ conductivity type gate (1).

    Transistor and circuit including a transistor
    8.
    发明公开
    Transistor and circuit including a transistor 失效
    晶体管，以及包含电路的晶体管。

    公开(公告)号：EP0092645A2

    公开(公告)日：1983-11-02

    申请号：EP83100929.5

    申请日：1983-02-01

    申请人： International Business Machines Corporation

    发明人： Solomon, Paul Michael

    IPC分类号： H01L29/10 ,  H01L29/72

    CPC分类号： H01L29/7606

    摘要： O A field induced base ballistic majority carrier transfer transistor comprises first and second epitaxial semi- conductor regions (1, 2) of the same conductivity type, the conductivity of the second region (2) being lower than that of the first region (1) and the second region having a lower energy bandgap than the first region. An emitter electrode (5) is connected, via a high conductivity region (3) epitaxial with the second region (2), to the side of the second region remote from the interface (8). A base electrode (6) makes contact with a part of the second region adjacent the interface (8), and a collector electrode (7) is connected to the side of the first region (1) remote from the interface (8).
    If the transistor is formed of n-type materials, application of a bias voltage across the emitter and base electrodes produces an accumulation layer (9) which serves as the base of the transistor, in the second region (2) adjacent the interface (8).