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    Multi-signal processor synchronized system
    1.
    发明公开
    Multi-signal processor synchronized system 失效
    Synchronisiertes Systemfürmehrere Signalprozessoren。

    公开(公告)号：EP0224626A1

    公开(公告)日：1987-06-10

    申请号：EP85430037.3

    申请日：1985-10-30

    申请人： International Business Machines Corporation ,  Compagnie IBM FRANCE

    发明人： Blanc, Alain ,  Jeanniot, Patrick ,  Spalmacin-Roma, Sylvie

    IPC分类号： H04B1/66 ,  G06F13/22

    CPC分类号： G06F9/4825 ,  G06F13/22 ,  H04B1/667 ,  H04J3/0626 ,  H04M1/253

    摘要： The system is made to concentrate n voice signals over a same high speed channel using a single Unit Processor.
    The data transfers between the Unit Processor and a set of Signal Processors are managed by a counter loaded by the Unit Processor with a predetermined value selected according to the system architecture. The counter is made of two parts serially connected , the first one made for sequentially providing an interrupt request to the Unit Processor and the second one driving a decoder providing signals for serially scanning the set of signal processors and providing time slots for data transfers between Unit Processor and Signal Processors.

    摘要翻译： 该系统通过使用单个单元处理器将n个语音信号集中在同一高速通道上。 单元处理器和一组信号处理器之间的数据传输由单元处理器加载的计数器以根据系统架构选择的预定值进行管理。 该计数器由串联连接的两个部分组成，第一个部分用于顺序地向单位处理器提供中断请求，第二个驱动解码器提供用于串行扫描该组信号处理器的信号，并提供用于在单元 处理器和信号处理器。

    Switching system comprising distributed elements allowing attachment to lines adapters
    5.
    发明公开
    Switching system comprising distributed elements allowing attachment to lines adapters 失效
    包括用于线路适配器的连接切换的系统，所述分布式元件

    公开(公告)号：EP0849916A3

    公开(公告)日：1998-12-16

    申请号：EP97480051.8

    申请日：1997-08-19

    申请人： International Business Machines Corporation

    发明人： Blanc, Alain ,  Saurel, Alain ,  Brezzo, Bernard ,  Poret, Michel

    IPC分类号： H04L12/56

    CPC分类号： H04L49/3081 ,  H04L49/1553 ,  H04L2012/5642 ,  H04Q11/0478

    摘要： A switching system comprising a switching structure (1130) for routing cells from a set of M input ports towards a set of M output ports. The systems further includes a set of distributed individual Switch Core Access Layer elements (S.C.A.L.) (1000) which communicating with one input and output port of the switching structure by means of a set of serial communication links (1400, 1600). Each SCAL element provides attachment to at least one Protocol Adapter (Protocol Engine 1600- 1900), and comprises a set of circuits (PINT 511-515; 611-614), each PINT circuit being associated with a corresponding one of said at least Protocol Adapter (Protocol Engine 1600-1900). The receive part of each circuit receives the data cells from the attached Protocol Adapter (Protocol Engine 1600) and includes at least one first FIFO storage (701-704) for storing the cells being received. Additionaly, there is introduced at least one extra byte to every cell, which at least one extra byte is reserved for a routing header dedicated for controlling either the routing process within the switching structure. Each transmit part of the destination PINT circuit comprises at least one second FIFO storage (801-802) having a substantially greater capacity than said of said first FIFO storage. Every Transmit part receives all the cells that are generated at the corresponding output port but uses the at least one extrabyte for determining whether or not the cell is to be entered into the at least second FIFO contained in a considered PINT circuit. Additionaly, each distributed individual SCAL element comprises control means for performing Time Division Multiplexing (TDM) access of the at least one first FIFO and second FIFO so that the high rate communication between the switching structure and SCALs can be distributed between the different Protocol Adapters. A set of serializer/deserializer permit the use of cheap serialized communication links between the centralized switching system and the different SCAL elements.

    Switching system comprising distributed elements allowing attachment to line adapters, and having multicasting capabilities
    6.
    发明公开
    Switching system comprising distributed elements allowing attachment to line adapters, and having multicasting capabilities 失效
    切换系统，用于连接到Leitungsanpassern和多个传输机会分布的元素

    公开(公告)号：EP0849973A2

    公开(公告)日：1998-06-24

    申请号：EP97480057.5

    申请日：1997-08-19

    申请人： International Business Machines Corporation

    发明人： Blanc, Alain ,  Nicolas, Laurent ,  Gohl, Sylvie

    IPC分类号： H04Q11/04

    CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L49/256 ,  H04L49/309 ,  H04L2012/5627 ,  H04L2012/5672 ,  H04L2012/5681 ,  H04Q11/0478

    摘要： A switching system comprising a switching structure (1130) for routing cells from a set of M input ports towards a set of M output ports. Each cell comprises a routing header defining to which of said M output ports the cell is to be routed. The system further includes a set of distributed individual Switch Core Access Layer elements (S.C.A.L.) ( 1000), each distributed SCAL element communicating through one communication link (1400, 1600) to the input and output port of the centralized switching structure (1130). Each SCAL element allows the attachment to at least one Protocol Adapter (Protocol Engine 1600- 1900) and comprises a set of corresponding PINT circuits which further includes a receive part receiving the data cells from the attached Protocol Adapter (Protocol Engine 1600). The receive part includes means for introducing at least one extra byte to every cell that will be reserved for carrying a routing header used for controlling the switching structure in a first step, then a second header that will be used for the PINT circuit when the cell will be received by the transmit part of the PINT element, in a second step. The transmit part of each PINT circuit comprises a control module that receives all the cells that are routed and generated at the considered output port. In accordance with the value carried by the extrabytes, the control means controls whether to discard or not the cell being presented at the input of the PINT circuit. While the receive part of the PINT circuit performs the introduction of the extrabytes needed for controlling the routing and multicasting operations, the accurate values that are needed for doing this are generated into the switching system by means of two successive table read operations. These two successive read operation achieves a two-level multicast feature that provides wide multicasting capabilities, even when the SCAL elements are distributed at different physical areas of the switching system.

    摘要翻译： 一种开关系统，包括用于从一组的M个输入端口向一组M个输出端口的路由单元的开关结构（1130）。 每个单元包括一个路由报头限定到的所述m个输出端口的电池是将被路由。 该系统还包括一组分布式个人交换机核心访问层元件（S.C.A.L.）（1000），每个分布式SCAL元件通过一个通信链路（1400，1600）到集中式交换结构（1130）的输入和输出端口进行通信。 每个SCAL元件允许附接至至少一个协议适配器（协议引擎1600- 1900）和包括一组PINT电路CORRESPONDING其进一步包括：接收部分，接收从连接的协议适配器（协议引擎1600）中的数据单元。 接收部分包括：用于引入至少一个额外的字节thatwill被用于执行用于在第一步骤中控制开关结构的路由报头保留每一个细胞，然后进行第二次头thatwill用于PINT电路当电池 将由PINT元件的发射部分被接收，在第二步骤中。 每个PINT电路的发射部分包括一个控制模块没有接收到所有的细胞都被路由并生成在所考虑的输出端口。在与由所述额外的字节所携带的值雅舞蹈，所述控制装置控制是否丢弃或不属于细胞呈现 在PINT电路的输入端。 虽然接收的PINT电路的一部分进行介绍需要用于控制所述路由和多播业务的额外字节的，需要精确的值并用于执行此操作是通过手段的两个连续的表读操作生成到交换系统。 这两个连续的读取操作实现了两电平的多播功能没有提供宽多播能力，即使当SCAL元件在该交换系统的不同物理区域分布。

    Decimation filter for a sigma-delta converter and an analog-to-digital converter using the same
    7.
    发明公开
    Decimation filter for a sigma-delta converter and an analog-to-digital converter using the same 失效
    Sigma-Delta Konverter和Datenendeinrichtung mit einem solchen Filter的Dezimationsfilter。

    公开(公告)号：EP0523306A1

    公开(公告)日：1993-01-20

    申请号：EP91480114.7

    申请日：1991-07-17

    申请人： International Business Machines Corporation

    发明人： Abbiate, Jean-Claude ,  Blanc, Alain ,  Jeanniot, Patrick ,  Orengo, Gérard ,  Richter, Gérard

    IPC分类号： H03H17/06

    CPC分类号： H03H17/0614 ,  H03H17/0664

    摘要： A decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock into a train of PCM samples which includes counting means (321, 331, 341) driven by the sigma-delta clock (fs) and which is continuously incremented by one during N sigma-delta clock pulses, then decremented by two during N following sigma-delta clock pulses and then incremented again by one during N following sigma-delta clock pulses in order to provide a sequence of incrementation parameter DELTA(n). The decimation filter further includes storing means (320, 330, 340) for storing the value of the coefficient C(n) corresponding to the decimation filter transfer function, and means (327, 337, 347) driven by the sigma-delta clock for incrementing the storing means with the incrementation parameter DELTA(n). At last, the decimation filter includes computing means (323, 333, 343, 327, 337, 347) for deriving from the contents C(n) of said storing means and from the train of input sigma-delta samples S(i+n) one Pulse Code Modulation (PCM) sample every 3xN input sigma-delta samples according to the formula:
    Since the coefficients C(n) are directly and on-line computed with the reception of the sigma-delta pulses, the decimation filter can operate for any value of the decimation parameter without requiring the use of substantial digital processing resources. The decimation filter can be used for a wide variety of different applications requiring different decimation factors.

    摘要翻译： 一种抽取滤波器，用于将与Σ-Δ时钟同步的一串Σ-Δ脉冲S（i）转换成PCM采样序列，其包括由Σ-Δ时钟（fs）驱动的计数装置（321,331,341） ），并且在N个Σ-Δ时钟脉冲期间连续地递增1，然后在N个跟随的Σ-Δ时钟脉冲期间递减2，然后在N个跟随的Σ-Δ时钟脉冲期间再次递增1，以便提供递增序列 参数DELTA（n）。 抽取滤波器还包括用于存储对应于抽取滤波器传递函数的系数C（n）的值的存储装置（320,330,340），以及由Σ-Δ时钟驱动的装置（327,337,347），用于 用递增参数DELTA（n）递增存储装置。 最后，抽取滤波器包括用于从所述存储装置的内容C（n）和从串行的输入Σ-Δ样本S（i + n）导出的计算装置（323,333,343,327,337,347） ）一个脉冲编码调制（PCM）根据以下公式每3×N个输入Σ-Δ样本进行采样：由于系数C（n）直接和在线计算，接收Σ-Δ脉冲，所以抽取 滤波器可以对抽取参数的任何值进行操作，而不需要使用实质的数字处理资源。 抽取滤波器可用于需要不同抽取因子的各种不同应用。

    Switching system comprising a mask mechanism for altering the internal routing process
    9.
    发明公开
    Switching system comprising a mask mechanism for altering the internal routing process 失效
    Vermittlungssystem mit einem Maskiermechanismus zurÄnderungdes internen Leitweglenkungsprozesses

    公开(公告)号：EP0961443A1

    公开(公告)日：1999-12-01

    申请号：EP98480041.7

    申请日：1998-05-29

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Blanc, Alain ,  Brezzo, Bernard ,  Saurel, Alain

    IPC分类号： H04L12/56

    CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/153 ,  H04L49/256 ,  H04L49/309 ,  H04L2012/5627 ,  H04L2012/5681

    摘要： A Switching system (15 or 25) receiving data cells from a set of n input ports and to be routed to one or more output ports in accordance with the contents of a bitmap value introduced in the cell at the entrance of said module, said module comprising a shared buffer for storing the cells which are to be routed. The systems further comprises a mask mechanism with a mask register for altering the value of the bitmap before it is used for controlling the routing process for either transporting the considered cell to the output port or discarding the latter. Two switching systems are combined in a first and a second Switch Fabrics (10, 20) in order to respectively form a first and second switch cores, located in a centralized building and a set of Switch Core Access Layer (S.C.A.L.) elements distributed in different physical areas. Each SCAL element respectively comprises a SCAL Receive element (11-i) and a SCAL Xmit element (12-i) for respectively permitting access to a corresponding input and output port of one of said switching system. A set of Port Adapters (30; 31) are distributed at different physical areas and are connected to said first and second Switch Fabrics via a particular SCAL element so that each Switching system (15, 25) receives the sequence of cells coming from any Port adapter and conversely any Port adapter may receive data from any one of said first or second switch cores. The mask achieves the distribution of the first and second switching systems between the different attached Port adapters, thus providing a load balancing between the two switching systems permitting to associate their individual buffering resources.

    摘要翻译： 1.一种从一组n个输入端口接收数据单元并根据在所述模块入口处的单元中引入的位图值的内容被路由到一个或多个输出端口的交换系统（15或25），所述模块 包括用于存储要路由的单元的共享缓冲器。 系统还包括具有掩模寄存器的掩模机构，用于在将位图的值用于控制用于将所考虑的单元传送到输出端口或丢弃该位图之前的路由处理。 两个交换系统组合在第一和第二交换结构（10,20）中，以便分别形成位于集中式建筑物中的第一和第二交换机核心，以及分布在不同网络中的一组交换机核心接入层（SCAL） 物理区域。 每个SCAL元件分别包括用于分别允许访问所述交换系统之一的相应输入和输出端口的SCAL接收元件（11-i）和SCAL Xmit元件（12-i）。 一组端口适配器（30; 31）分布在不同的物理区域，并且通过特定的SCAL元件连接到所述第一和第二交换结构，使得每个交换系统（15,25）接收来自任何端口的单元序列 适配器，并且相反地，任何端口适配器可以从所述第一或第二交换机核心中的任何一个接收数据。 掩模实现了在不同的附接端口适配器之间的第一和第二交换系统的分布，从而在允许关联其各自的缓冲资源的两个交换系统之间提供负载平衡。

    Switching system
    10.
    发明公开
    Switching system 失效
    交换系统

    公开(公告)号：EP0849917A3

    公开(公告)日：1998-12-16

    申请号：EP97480056.7

    申请日：1997-08-19

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Blanc, Alain ,  Robbe, Jean-Claude ,  Landry, Christian ,  Poret, Michel

    IPC分类号： H04L12/56

    CPC分类号： H04L12/5601 ,  H04L49/203 ,  H04L49/309 ,  H04L2012/5625 ,  H04L2012/563 ,  H04L2012/5652 ,  H04L2012/5681

    摘要： A switching module including a storage section that comprises a set of M receiver means (10), a set of M input routers (2) for realizing the connection of the M input ports to anyone of the different locations of a cell storage (1). The storage section includes a set of M ASA registers (20, 21) for providing to input routers (2) with the addresses to be used for storing the cells into the cell storage (1). Additionaly, the switching module includes a retrieve section that comprises a set of M output routers for retrieving the data located into any locations of said cell storage (1), a set of M ARA registers for providing to said output routers (3) the addresses of the cells which are to be outputted from said cell storage. Further, a specific control section provides with the input process and the output process of the cells that are entered into the switch. The input control section address generating means (FAQ 5) for providing the addresses of the empty locations into cell storage (1) and first multiplexing means (106, 107, 112, 113) for providing either the addresses generated by said address generating means (FAQ 5) or addresses provided by a first external bus (509, 510) to said M ASA registers (20, 21). A set of holding registers (60, 63) is used for retaining the module routing header as long as the cells are being inputted in the cell storage (1). The output control section comprises a set of M queueing means (OAQ 50, 51) for queueing the addresses of the locations within said cell storage (1) that contains cells that are to be transmitted to output ports. Each queuing means has an input receiving the contents of said ASA registers (20, 21) and is associated to a corresponding one of said M output ports. Additionaly control means (150, 200) receive the module routing header retained by the holding registers and generate control signals (WEs, 210) for all the queuing means (50, 51) so that the contents of said ASA registers can be simultaneously loaded into the particular queuing means (OAQ queues 50, 51) that corresponds to the ouput ports according to the module routing header, that is to say in accordance with the particular output ports to which the cell should be duplicated. Second multiplexing means (800, 26, 27) are provided so as to provide to said M ARA registers either with addresses provided by the queuing means (OAQ 50, 51) or the addresses provided by a second external bus (520, 521). A specific registration circuit (7) is used for preventing an address into cell storage (1) to be made available as long as the last occurence of the considered address disappear from the contents of the queuing means. By means ofthe first and second multiplexor it becomes possible to realize the routing process internally or externally. Indeed, the addresses that are used for performing both the input and output process may either be generated by means of the internally located circuits, including the addresses generating means and control circuit (200), or still may be achieved by means of an external circuitry (with the respect to the module being considered).

    摘要翻译： 一种包括存储部分的交换模块，该存储部分包括一组M个接收器装置（10），一组M个输入路由器（2），用于实现将M个输入端口连接到单元存储器（1）的不同位置中的任何一个， 。 存储部分包括一组M ASA寄存器（20,21），用于向输入路由器（2）提供要用于将信元存储到信元存储器（1）中的地址。 另外，切换模块包括：检索部分，其包括用于检索位于所述单元存储器（1）的任何位置的数据的一组M个输出路由器，用于向所述输出路由器（3）提供地址的一组MARA寄存器 将从所述细胞存储器输出的细胞。 此外，特定的控制部分提供输入到开关中的单元的输入过程和输出过程。 用于将空位置的地址提供给单元存储器（1）的输入控制部分地址产生装置（FAQ 5）和第一多路复用装置（106,107,112,113），用于提供由所述地址产生装置（ （5）或由第一外部总线（509,510）提供给所述M个ASA寄存器（20,21）的地址。 只要单元正被输入到单元存储器（1）中，一组保持寄存器（60,63）用于保持模块路由头。 输出控制部分包括一组M个排队装置（OAQ 50,51），用于排队所述单元存储器（1）内包含将被发送到输出端口的单元的位置的地址。 每个排队装置具有接收所述ASA寄存器（20,21）的内容并且与所述M个输出端口中对应的一个输出端口相关联的输入。 附加控制装置（150,200）接收由保持寄存器保持的模块路由报头并为所有排队装置（50,51）产生控制信号（WEs，210），使得所述ASA寄存器的内容可以同时加载到 根据模块路由报头，也就是说根据应该复制单元的特定输出端口，对应于输出端口的特定排队装置（OAQ队列50,51）。 提供第二多路复用装置（800,26,27），以便向所述M个ARA寄存器提供由排队装置（OAQ 50,51）提供的地址或由第二外部总线（520,521）提供的地址。 只要所考虑的地址的最后一次出现从排队装置的内容中消失，就使用特定的登记电路（7）来防止地址进入单元存储（1）。 通过第一和第二多路复用器，可以在内部或外部实现路由选择过程。 事实上，用于执行输入和输出过程的地址可以通过包括地址生成装置和控制电路（200）的内部定位电路来生成，或者仍然可以通过外部电路 （关于正在考虑的模块）。