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17 条记录 (耗时 0.014 秒)

    A method of filling shallow trenches
    2.
    发明公开
    A method of filling shallow trenches 失效
    Verfahren zumFüllenvon nicht tiefen Graben

    公开(公告)号：EP0872885A2

    公开(公告)日：1998-10-21

    申请号：EP98301844.1

    申请日：1998-03-12

    申请人： International Business Machines Corporation ,  SIEMENS AKTIENGESELLSCHAFT

    发明人： Fiegl, Bernhard ,  Glashauser, Walter ,  Levy, Max G. ,  Nastasi, Victor R,

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76224 ,  H01L21/31053

    摘要： A method of isolation in silicon integrated circuit processing overfills the trench by a fill margin, deposits a temporary layer of poly (120) having a thickness less than the trench depth by the thickness of an oxide polish stop (130), so that the top of the polish stop is coplanar with the top of the fill layer outside the trench; the temporary layer is polished outside the trench, using the fill layer and the polish stop layer (130) as polish stops; the polish stop layer is removed together with the same thickness of the fill layer and temporary layer, preserving planarity that is destroyed by selectively etching the fill layer; the remaining temporary layer is stripped and a final touch up polish of the fill layer stops on the pad nitride.

    摘要翻译： 将衬底中的平面化平坦化到参考表面的方法包括沉积比沟槽更厚的填充层（110）并且在参考表面上方并且沉积具有沟槽深度的厚度减去一个的临时填充层（120） 抛光边缘高于参考面。 沉积具有抛光边缘厚度的抛光阻挡层（130）和形成的抛光掩模（40）。 停止层被去除在掩模之外，并且临时层被抛光以使上表面与第一填充层的顶表面共面。 蚀刻停止层和临时层，去除抛光停止层并在沟槽上方留下填充层的盖，并保留中间平面。 然后通过蚀刻覆盖层外部的填充层而使其破坏，使得第二填充顶表面与沟槽中的第一填充层共面。 然后蚀刻临时填充层，留下第一填充层，然后抛光，停止在参考表面上。

    A method of manufacturing an insulated gate field effect transistor
    3.
    发明公开
    A method of manufacturing an insulated gate field effect transistor 失效
    用绝缘栅场效应晶体管的制造方法

    公开(公告)号：EP0822593A3

    公开(公告)日：1998-04-15

    申请号：EP97305279.8

    申请日：1997-07-15

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  SIEMENS AKTIENGESELLSCHAFT

    发明人： Haue, Manfred ,  Levy, Max G. ,  Nastasi, Victor Ray

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10873 ,  H01L27/10829

    摘要： A Field Effect Transistor (FET) and a method of forming FETs on a silicon wafer. First, trenches are formed in a surface of the silicon wafer. An ONO layer is formed on the surface, lining the trenches. Potassium is diffused along the ONO layer. Part of the ONO layer is removed to expose the wafer surface with the ONO layer remaining in the trenches. Gate oxide is formed on the exposed wafer surface. Finally, FET gates are formed on the gate oxide. Preferably, potassium is introduced during Chem-Mech polish when the trenches are filled with polysilicon. A slurry containing KOH is used to polish the polysilicon and the potassium diffuses from the slurry along the ONO layer. After chem-Mech polish, the poly in the trenches is recessed by Reactive Ion Etching (RIE) it below the wafer surface. Optionally, after RIE, the wafer may be dipped in a KOH solution. Next, an oxide collar is formed along the ONO layer in the trenches above the recessed polysilicon. The recesses are filled by a second layer of polysilicon that is Chem-Mech polished with the same slurry to remove polysilicon from the wafer surface. The polished polysilicon may be Reactive Ion etched until it is essentially coplanar with the wafer surface. The resulting FET has thicker gate oxide along its sides than in the center of its channel.

    A method of manufacturing an insulated gate field effect transistor
    5.
    发明公开
    A method of manufacturing an insulated gate field effect transistor 失效
    一种制造绝缘栅场效应晶体管的方法

    公开(公告)号：EP0822593A2

    公开(公告)日：1998-02-04

    申请号：EP97305279.8

    申请日：1997-07-15

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  SIEMENS AKTIENGESELLSCHAFT

    发明人： Haue, Manfred ,  Levy, Max G. ,  Nastasi, Victor Ray

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10873 ,  H01L27/10829

    摘要： A Field Effect Transistor (FET) and a method of forming FETs on a silicon wafer. First, trenches are formed in a surface of the silicon wafer. An ONO layer is formed on the surface, lining the trenches. Potassium is diffused along the ONO layer. Part of the ONO layer is removed to expose the wafer surface with the ONO layer remaining in the trenches. Gate oxide is formed on the exposed wafer surface. Finally, FET gates are formed on the gate oxide. Preferably, potassium is introduced during Chem-Mech polish when the trenches are filled with polysilicon. A slurry containing KOH is used to polish the polysilicon and the potassium diffuses from the slurry along the ONO layer. After chem-Mech polish, the poly in the trenches is recessed by Reactive Ion Etching (RIE) it below the wafer surface. Optionally, after RIE, the wafer may be dipped in a KOH solution. Next, an oxide collar is formed along the ONO layer in the trenches above the recessed polysilicon. The recesses are filled by a second layer of polysilicon that is Chem-Mech polished with the same slurry to remove polysilicon from the wafer surface. The polished polysilicon may be Reactive Ion etched until it is essentially coplanar with the wafer surface. The resulting FET has thicker gate oxide along its sides than in the center of its channel.

    摘要翻译： 场效应晶体管（FET）和在硅晶片上形成FET的方法。 首先，在硅晶片的表面上形成沟槽。 在表面上形成ONO层，衬里沟槽。 钾沿着ONO层扩散。 部分ONO层被去除以暴露晶片表面，ONO层保留在沟槽中。 栅极氧化物形成在暴露的晶片表面上。 最后，FET栅极形成在栅极氧化物上。 优选地，当沟槽用多晶硅填充时，在Chem-Mech抛光期间引入钾。 使用含有KOH的浆料来抛光多晶硅和钾沿着ONO层从浆料中扩散。 在化学机械抛光之后，沟槽中的多晶硅通过反应离子蚀刻（RIE）在晶圆表面下方凹陷。 可选地，在RIE之后，可以将晶片浸入KOH溶液中。 接下来，沿凹槽多晶硅上方的沟槽中的ONO层形成氧化物环。 凹槽由第二层多晶硅填充，该第二层多晶硅用相同的浆料进行Chem-Mech抛光以从晶片表面去除多晶硅。 抛光的多晶硅可以被反应离子蚀刻直到它基本上与晶片表面共面。 由此产生的FET沿其两侧的栅氧化层比其沟道中央厚。

    Insulated gate field effect transistor
    6.
    发明公开
    Insulated gate field effect transistor 失效
    Feldeffekttransistor mit isolerter Steuerelektrode

    公开(公告)号：EP0822591A1

    公开(公告)日：1998-02-04

    申请号：EP97305281.4

    申请日：1997-07-15

    申请人： International Business Machines Corporation ,  SIEMENS AKTIENGESELLSCHAFT

    发明人： Hauf, Manfred ,  Levy, Max G. ,  Nastasi, Victor Ray

    IPC分类号： H01L21/763 ,  H01L27/108

    CPC分类号： H01L27/10861 ,  H01L21/3105 ,  H01L21/763

    摘要： An FET isolated on either side by a trench. The FET has a dielectric layer in the isolating trench along at least one side. The dielectric layer which may be an ONO layer has an oxidation catalyst diffused into it. The oxidation catalyst may be potassium. Gate oxide along the side of the FET in close proximity to the ONO layer is thicker than gate oxide between both sides.

    摘要翻译： 一个FET通过沟槽隔离在任一侧。 FET在至少一侧的隔离沟槽中具有介电层。 可以是ONO层的电介质层具有扩散到其中的氧化催化剂。 氧化催化剂可以是钾。 靠近ONO层的FET侧的栅极氧化物比两侧之间的栅极氧化物厚。

    Methods for protecting device components from chemical mechanical polish induced defects
    10.
    发明公开
    Methods for protecting device components from chemical mechanical polish induced defects 失效
    保护设备部件免受化学机械抛光引起的缺陷的方法

    公开(公告)号：EP0910117A3

    公开(公告)日：1999-06-02

    申请号：EP98305084.0

    申请日：1998-06-26

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Levy, Max G. ,  Fiegl, Bernhard ,  Bergner, Wolfgang ,  Goth, George R. ,  Parries, Paul ,  Sendelbach, Matthew J. ,  Wang, Ting-Hao ,  Wille, William C. ,  Wittmann, Juergen

    IPC分类号： H01L21/3105

    CPC分类号： H01L21/31053

    摘要： A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.

    摘要翻译： 一种用于防止CMP引起的（化学机械抛光）损坏设置在台面的垫氮化物层下方的衬底的方法。 垫氮化物层设置在共形沉积的电介质层下方。 介电层设置在共形沉积的多晶硅层下方。 该方法包括使用CMP将多晶硅层平坦化到至少介电层的表面以暴露介电层的第一区域。 该方法还包括使用第一蚀刻参数部分地蚀刻介电层的第一区域。 第一蚀刻参数包括对衬垫氮化物层基本上具有选择性的蚀刻剂源气体，以防止衬垫氮化物层即使在存在CMP缺陷的情况下也被蚀刻穿过。 此外，还包括在蚀刻之后部分地通过介电层的第一区域去除多晶硅层。