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    Method and structure for reducing power noise
    1.
    发明公开
    Method and structure for reducing power noise 有权
    Verfahren und Struktur zur Reduzierung des Leistungsrauschens

    公开(公告)号：EP1111969A1

    公开(公告)日：2001-06-27

    申请号：EP00126690.7

    申请日：2000-12-05

    申请人： International Business Machines Corporation

    发明人： Frech, Roland, Dr. ,  Klink, Erich ,  Rehm, Simone ,  Virag, Helmut ,  Winkel, Thomas-Michael, Dr. ,  Chamberlin, Bruce ,  Becker, Wiren Dale ,  Ma, Wai Mon

    IPC分类号： H05K1/02 ,  H05K1/11

    CPC分类号： H05K1/113 ,  H05K1/0231 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/0979 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611

    摘要： Described is a method for minimizing switching noise in the high and mid-frequency range on printed circuit cards or boards by means of a plurality of surface mounted decoupling capacitors (4). A novel configuration and implementation of capacitor pads (2) including the connecting vias (6) is also presented. As a result the parasitic inductance of the pads and vias can be significantly reduced. Thus the effectiveness of the decoupling capacitors in the mid and high frequency range can be increased, the voltage drop can be reduced and the system performance can be increased. Several design rules for the new pad via configuration lead to the significant reduction of the parasitic inductance. The proposal is especially important for high integrated system designs on boards and cards combined with increased cycle times.

    摘要翻译： 描述了一种通过多个表面安装的去耦电容器（4）最小化印刷电路板或板上的高频和中频范围内的开关噪声的方法。 还提出了包括连接通孔（6）的电容器焊盘（2）的新颖配置和实现。 结果，焊盘和通孔的寄生电感可以显着降低。 因此，可以提高中高频区域中的去耦电容器的有效性，可以降低电压降并且可以提高系统性能。 通过配置的新焊盘的几个设计规则导致寄生电感的显着降低。 该建议对于板卡和卡上的高集成系统设计以及增加的周期时间尤其重要。