公开(公告)号：EP0023972B1

公开(公告)日：1984-12-05

申请号：EP80103967.8

申请日：1980-07-10

申请人： International Business Machines Corporation

发明人： Das Gupta, Sumit ,  Goel, Prabhakar ,  Williams, Thomas Walter

IPC分类号： G06F11/26

CPC分类号： G01R31/318541 ,  G01R31/318583

公开(公告)号：EP0023972A3

公开(公告)日：1981-08-26

申请号：EP80103967

申请日：1980-07-10

申请人： International Business Machines Corporation

发明人： Das Gupta, Sumit ,  Goel, Prabhakar ,  Williams, Thomas Walter

IPC分类号： G06F11/26

CPC分类号： G01R31/318541 ,  G01R31/318583

摘要： According to the invention, the LSI testing methods allow the states of combinational logic networks to be captured in either a group of master latches (390) or slave latches (400) of shift registers used for performing scan-in scan-out operations on test data (test patterns, result patterns), but not both. If on a particular test the states are captured in the master latches, then each master latch state is subsequently shifted to the corresponding slave latch by the application of a shift clock, as known from the art. If instead the states are captured in the slave latches the slave latches can be immediately shifted out for inspection.

公开(公告)号：EP0023972A2

公开(公告)日：1981-02-18

申请号：EP80103967.8

申请日：1980-07-10

申请人： International Business Machines Corporation

发明人： Das Gupta, Sumit ,  Goel, Prabhakar ,  Williams, Thomas Walter

IPC分类号： G06F11/26

CPC分类号： G01R31/318541 ,  G01R31/318583

摘要： According to the invention, the LSI testing methods allow the states of combinational logic networks to be captured in either a group of master latches (390) or slave latches (400) of shift registers used for performing scan-in scan-out operations on test data (test patterns, result patterns), but not both.
If on a particular test the states are captured in the master latches, then each master latch state is subsequently shifted to the corresponding slave latch by the application of a shift clock, as known from the art.
If instead the states are captured in the slave latches the slave latches can be immediately shifted out for inspection.

摘要翻译： 根据本发明，LSI测试方法允许组合逻辑网络的状态被捕获在用于执行扫描/扫描输出操作的移位寄存器的一组主锁存器（390）或从锁存器（400）中 测试数据（测试模式，结果模式），但不能同时复位，如果在特定测试中，状态被捕获在主锁存器中，则每个主锁存状态随后通过应用 如本领域已知的移位时钟。 ... 如果在从锁存器中捕获状态，则可以将从动锁存器立即移出来进行检查。