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公开(公告)号：EP0023972A3
公开(公告)日：1981-08-26
申请号：EP80103967
申请日：1980-07-10
IPC分类号： G06F11/26
CPC分类号： G01R31/318541 , G01R31/318583
摘要： According to the invention, the LSI testing methods allow the states of combinational logic networks to be captured in either a group of master latches (390) or slave latches (400) of shift registers used for performing scan-in scan-out operations on test data (test patterns, result patterns), but not both. If on a particular test the states are captured in the master latches, then each master latch state is subsequently shifted to the corresponding slave latch by the application of a shift clock, as known from the art. If instead the states are captured in the slave latches the slave latches can be immediately shifted out for inspection.
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公开(公告)号：EP0023972B1
公开(公告)日：1984-12-05
申请号：EP80103967.8
申请日：1980-07-10
IPC分类号： G06F11/26
CPC分类号： G01R31/318541 , G01R31/318583
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3.发明公开Shift register latch circuit operable as a D-type edge trigger and counter comprising a plurality of such latch circuits 失效移在D触发器和计数器由多个这样的移位寄存器锁存器的的方式寄存器锁存电路。
公开(公告)号：EP0010599A1
公开(公告)日：1980-05-14
申请号：EP79103405.1
申请日：1979-09-12
发明人： Brown, David John , Walther, Ronald G. , Williams, Thomas Walter , Wrigglesworth, Michael Denis
摘要： A shift register latch circuit consists of a polarity hold latch (1) connected to a set/reset latch (2). The latches can be clocked with separate non-overlapping clock trains (+A, +B and +C) so that automatically generated test patterns can be applied to a scan input (s) to test the circuit. This conforms to the so-called Level Sensitive Scan Design (LSSD) rules. During system operation, the shift register latch circuit operates as a " D" type edge trigger by connecting the clock input (+ B) of the set/reset latch (2) to the clock (-C) supplied to the polarity hold latch (1). By connecting a number of shift register latches together a Johnson counter can be formed and by clocking all latches with a single oscillator, a series of non-overlapping clock trains can be produced. Implementations of the shift register latch in AND circuits or AND OR INVERT circuits are described.
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4.发明授权Shift register latch circuit operable as a D-type edge trigger and counter comprising a plurality of such latch circuits 失效移位寄存器电路作为D型边缘触发器和包含多个这种锁存电路的计数器可操作
公开(公告)号：EP0010599B1
公开(公告)日：1982-05-05
申请号：EP79103405.1
申请日：1979-09-12
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5.发明公开A system of functional units for performing logic functions 失效系统funktioneller Einheiten zurDurchführunglogischer Funktionen。
公开(公告)号：EP0023972A2
公开(公告)日：1981-02-18
申请号：EP80103967.8
申请日：1980-07-10
IPC分类号： G06F11/26
CPC分类号： G01R31/318541 , G01R31/318583
摘要： According to the invention, the LSI testing methods allow the states of combinational logic networks to be captured in either a group of master latches (390) or slave latches (400) of shift registers used for performing scan-in scan-out operations on test data (test patterns, result patterns), but not both.
If on a particular test the states are captured in the master latches, then each master latch state is subsequently shifted to the corresponding slave latch by the application of a shift clock, as known from the art.
If instead the states are captured in the slave latches the slave latches can be immediately shifted out for inspection.摘要翻译： 根据本发明，LSI测试方法允许组合逻辑网络的状态被捕获在用于执行扫描/扫描输出操作的移位寄存器的一组主锁存器（390）或从锁存器（400）中 测试数据（测试模式，结果模式），但不能同时复位，如果在特定测试中，状态被捕获在主锁存器中，则每个主锁存状态随后通过应用 如本领域已知的移位时钟。 ... 如果在从锁存器中捕获状态，则可以将从动锁存器立即移出来进行检查。
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