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2.发明公开INSTRUCTIONS CONTROLLING ACCESS TO SHARED REGISTERS OF A MULTI-THREADED PROCESSOR 审中-公开说明控制对多线程处理器的共享寄存器的访问
公开(公告)号：EP3213188A1
公开(公告)日：2017-09-06
申请号：EP15787164.1
申请日：2015-10-21
发明人： SLEGEL, Timothy , BIRAN, Giora , BUSABA, Fadi, Yusuf , EREZ, Ophir , MESH, Alexander , FARRELL, Mark , HELLER, Lisa , JACOBI, Christian
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30021 , G06F9/30029 , G06F9/3004 , G06F9/30087 , G06F9/3009 , G06F9/3012 , G06F9/3851 , G06F9/46 , G06F2209/521
摘要： Atomic instructions, including a Compare And Swap Register, a Load and AND Register, and a Load and OR Register instruction, use registers instead of storage to communicate and share information in a multi-threaded processor. The registers are accessible to multiple threads of the multi-threaded processor, and the instructions operate on these shared registers. Access to the shared registers is controlled by the instructions via interlocking.
摘要翻译： 原子指令（包括比较和交换寄存器，加载和AND寄存器以及加载和OR寄存器指令）使用寄存器而不是存储器来在多线程处理器中进行通信和共享信息。 寄存器可以被多线程处理器的多个线程访问，并且指令在这些共享寄存器上运行。 访问共享寄存器由指令通过互锁来控制。
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公开(公告)号：EP1588267A1
公开(公告)日：2005-10-26
申请号：EP04731399.4
申请日：2004-05-06
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F9/30047 , G06F9/3824 , G06F12/1009 , G06F12/1036 , G06F12/109 , G06F2212/683
摘要： Selected units of storage, such as segments of storage or regions of storage, are invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure entries corresponding to the units of storage to be invalidated. Additionally, buffer entries associated with the invalidated units of storage or other chosen units of storage are cleared. An instruction is provided to perform the invalidation and/or clearing. Moreover, buffer entries associated with a particular address space are cleared, without any invalidation. This is also performed by the instruction. The instruction can be implemented in software, hardware, firmware or some combination thereof, or it can be emulated.
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公开(公告)号：EP2229632B1
公开(公告)日：2013-04-10
申请号：EP09700829.6
申请日：2009-01-05
发明人： GREINER, Dan , GAINEY, Charles Jr. , HELLER, Lisa , OSISEK, Damian , PFEFFER, Erwin , SLEGEL, Timothy , WEBB, Charles
CPC分类号： G06F12/1027 , G06F9/30047 , G06F12/0215 , G06F12/1009 , G06F12/1036 , G06F12/145 , G06F2212/1052 , G06F2212/654 , G06F2212/656 , G06F2212/68
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being executed. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field.
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公开(公告)号：EP2229632A1
公开(公告)日：2010-09-22
申请号：EP09700829.6
申请日：2009-01-05
发明人： GREINER, Dan , GAINEY, Charles Jr. , HELLER, Lisa , OSISEK, Damian , PFEFFER, Erwin , SLEGEL, Timothy , WEBB, Charles
CPC分类号： G06F12/1027 , G06F9/30047 , G06F12/0215 , G06F12/1009 , G06F12/1036 , G06F12/145 , G06F2212/1052 , G06F2212/654 , G06F2212/656 , G06F2212/68
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being executed. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field.
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公开(公告)号：EP1588267B1
公开(公告)日：2008-01-02
申请号：EP04731399.4
申请日：2004-05-06
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F9/30047 , G06F9/3824 , G06F12/1009 , G06F12/1036 , G06F12/109 , G06F2212/683
摘要： Selected units of storage, such as segments of storage or regions of storage, are invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure entries corresponding to the units of storage to be invalidated. Additionally, buffer entries associated with the invalidated units of storage or other chosen units of storage are cleared. An instruction is provided to perform the invalidation and/or clearing. Moreover, buffer entries associated with a particular address space are cleared, without any invalidation. This is also performed by the instruction. The instruction can be implemented in software, hardware, firmware or some combination thereof, or it can be emulated.
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公开(公告)号：EP1653343A3
公开(公告)日：2006-07-19
申请号：EP05108510.8
申请日：2004-05-06
CPC分类号： G06F12/1027 , G06F9/30047 , G06F9/3824 , G06F12/1009 , G06F12/1036 , G06F12/109 , G06F2212/683
摘要： Selected units of storage, such as segments of storage or regions of storage, are invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure entries corresponding to the units of storage to be invalidated. Additionally, buffer entries associated with the invalidated units of storage or other chosen units of storage are cleared. An instruction is provided to perform the invalidation and/or clearing. Moreover, buffer entries associated with a particular address space are cleared, without any invalidation. This is also performed by the instruction. The instruction can be implemented in software, hardware, firmware or some combination thereof, or it can be emulated.
摘要翻译： 选定的存储单元（如存储段或存储区域）将失效。 通过设置位于与要失效的存储单元相对应的数据结构条目中的失效指示符来促进失效。 另外，与被无效的存储单元或其他选择的存储单元相关联的缓冲区条目被清除。 提供执行无效和/或清除的指令。 此外，与特定地址空间相关联的缓冲区条目被清除，而没有任何失效。 这也是由指令执行的。 该指令可以用软件，硬件，固件或其组合来实现，或者可以被仿真。
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公开(公告)号：EP4396676A1
公开(公告)日：2024-07-10
申请号：EP22769224.1
申请日：2022-08-25
发明人： BUSABA, Fadi , HELLER, Lisa , FRANK, Janosch Andreas , BORNTRAEGER, Christian , BRADBURY, Jonathan
IPC分类号： G06F9/455
CPC分类号： G06F9/45558 , G06F2009/4558720130101 , G06F2009/4558320130101
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公开(公告)号：EP3935549A1
公开(公告)日：2022-01-12
申请号：EP20707411.3
申请日：2020-02-26
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公开(公告)号：EP3935546A1
公开(公告)日：2022-01-12
申请号：EP20709572.0
申请日：2020-03-06
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