摘要:
The system comprises at least one central processing (10, 12), a plurality of input/output terminals (14) and at least one control unit (16) having a plurality of ports (40, 42) each being connected to an input output terminal (14) for interfacing it with at least one central processing unit (10, 12). Each input/output terminal comprises a plurality of support logic means connected to one of the ports (40, 42) of the control unit (16), a buffer to each support logic means for storing data received from or to be transmitted to a central processing unit (10, 12), a text processor (38), a keyboard connected to the text processor (38) for effecting processing of link data and a printer and display (36, 48, 56) for outputting data and text character information. This structure allows the text processor (38) in the input/output terminal (14) to simultaneously, yet independently, emulate a display and printer normally associated with a host central processing unit.
摘要:
The system comprises at least one central processing (10, 12), a plurality of input/output terminals (14) and at least one control unit (16) having a plurality of ports (40, 42) each being connected to an input output terminal (14) for interfacing it with at least one central processing unit (10, 12). Each input/output terminal comprises a plurality of support logic means connected to one of the ports (40, 42) of the control unit (16), a buffer to each support logic means for storing data received from or to be transmitted to a central processing unit (10, 12), a text processor (38), a keyboard connected to the text processor (38) for effecting processing of link data and a printer and display (36, 48, 56) for outputting data and text character information. This structure allows the text processor (38) in the input/output terminal (14) to simultaneously, yet independently, emulate a display and printer normally associated with a host central processing unit.
摘要:
Word processing systems wherein material to be printed is formatted on a plurality of display units having each a display (22), and a text formatting processor (14) which formats the display material, the display units sharing a single printer (10). This is accomplished by having at least one of the display units called the primary display unit (11) which comprises means for controlling the sharing of the printer (10) by the other display units, and each of the other display units which communicates with the printer under the control of these printer sharing control means and through a printer sharing adapter (28). At least part of this printer sharing control means is contained in the text formatting processor (14) of the primary display unit (11).
摘要:
A communication bit pattern detection circuit that provides an output signal upon the occurrence of one of several predefined bit patterns for a series of a specified number of bits for a multiple of input signals where each input signal is a continuous stream of serial bit data. The communication bit pattern detection circuit includes a detection stage (39) having combinational logic connected to receive the input signals and providing the logically combined bits to latches (34,46,50,58) of a shift register. The number of latches in the shift register is less than the specified number of bits for the predefined bit patterns. The output of these latches are provided to a logic stage (63) that includes additional combinational logic that provides a nondetection signal. This nondetection signal is provided to indicate that the bits received are not part of any of the predefined bit patterns. The nondetection signal is input to reset a counter (70). The output of the counter is decoded to provide a signal when the counter counts to the specified number of bits in the predefined bit patterns.
摘要:
A communication bit pattern detection circuit that provides an output signal upon the occurrence of one of several predefined bit patterns for a series of a specified number of bits for a multiple of input signals where each input signal is a continuous stream of serial bit data. The communication bit pattern detection circuit includes a detection stage (39) having combinational logic connected to receive the input signals and providing the logically combined bits to latches (34,46,50,58) of a shift register. The number of latches in the shift register is less than the specified number of bits for the predefined bit patterns. The output of these latches are provided to a logic stage (63) that includes additional combinational logic that provides a nondetection signal. This nondetection signal is provided to indicate that the bits received are not part of any of the predefined bit patterns. The nondetection signal is input to reset a counter (70). The output of the counter is decoded to provide a signal when the counter counts to the specified number of bits in the predefined bit patterns.