公开(公告)号：EP0125411A3

公开(公告)日：1986-09-03

申请号：EP84102532

申请日：1984-03-09

Applicant: International Business Machines Corporation

Inventor： Mueller, Mark Wayne ,  Hill, Kevin Lynn ,  Hunt, Garyn Thomas ,  Smetana, Ronald ,  McVey, James Michael ,  Miller, Ernest Lee ,  Clements, Silous Floyd

IPC: G06F15/20

CPC classification number: G06F17/21

Abstract: The system comprises at least one central processing (10, 12), a plurality of input/output terminals (14) and at least one control unit (16) having a plurality of ports (40, 42) each being connected to an input output terminal (14) for interfacing it with at least one central processing unit (10, 12). Each input/output terminal comprises a plurality of support logic means connected to one of the ports (40, 42) of the control unit (16), a buffer to each support logic means for storing data received from or to be transmitted to a central processing unit (10, 12), a text processor (38), a keyboard connected to the text processor (38) for effecting processing of link data and a printer and display (36, 48, 56) for outputting data and text character information. This structure allows the text processor (38) in the input/output terminal (14) to simultaneously, yet independently, emulate a display and printer normally associated with a host central processing unit.

公开(公告)号：EP0125411B1

公开(公告)日：1991-06-26

申请号：EP84102532.3

申请日：1984-03-09

Applicant: International Business Machines Corporation

Inventor： Mueller, Mark Wayne ,  Hill, Kevin Lynn ,  Hunt, Garyn Thomas ,  Smetana, Ronald ,  McVey, James Michael ,  Miller, Ernest Lee ,  Clements, Silous Floyd

IPC: G06F15/20

CPC classification number: G06F17/21

公开(公告)号：EP0067310B1

公开(公告)日：1986-09-10

申请号：EP82104116.7

申请日：1982-05-12

Applicant: International Business Machines Corporation

Inventor： Mueller, Mark Wayne ,  Parker, Thomas Shelton

IPC: H04L5/14 ,  H03M9/00

CPC classification number: H04L5/1423 ,  H04L1/0083

公开(公告)号：EP0067283B1

公开(公告)日：1985-11-21

申请号：EP82103174.7

申请日：1982-04-15

Applicant: International Business Machines Corporation

Inventor： Mueller, Mark Wayne ,  Parker, Thomas Shelton ,  Benignus, Douglas Marvin ,  Frye, James Lee

IPC: G06F13/00

CPC classification number: G06F13/385

公开(公告)号：EP0125411A2

公开(公告)日：1984-11-21

申请号：EP84102532.3

申请日：1984-03-09

Applicant: International Business Machines Corporation

Inventor： Mueller, Mark Wayne ,  Hill, Kevin Lynn ,  Hunt, Garyn Thomas ,  Smetana, Ronald ,  McVey, James Michael ,  Miller, Ernest Lee ,  Clements, Silous Floyd

IPC: G06F15/20

CPC classification number: G06F17/21

Abstract: The system comprises at least one central processing (10, 12), a plurality of input/output terminals (14) and at least one control unit (16) having a plurality of ports (40, 42) each being connected to an input output terminal (14) for interfacing it with at least one central processing unit (10, 12). Each input/output terminal comprises a plurality of support logic means connected to one of the ports (40, 42) of the control unit (16), a buffer to each support logic means for storing data received from or to be transmitted to a central processing unit (10, 12), a text processor (38), a keyboard connected to the text processor (38) for effecting processing of link data and a printer and display (36, 48, 56) for outputting data and text character information. This structure allows the text processor (38) in the input/output terminal (14) to simultaneously, yet independently, emulate a display and printer normally associated with a host central processing unit.

Abstract translation: 该系统包括至少一个中央处理（10,12），多个输入/输出端子（14）和至少一个具有多个端口（40,42）的控制单元（16），每个端口连接到输入输出端 终端（14），用于将其与至少一个中央处理单元（10,12）对接。 每个输入/输出终端包括连接到控制单元（16）的端口（40,42）中的一个的多个支持逻辑装置，每个支持逻辑装置的缓冲器，用于存储从或将发送到中央的数据 处理单元（10,12），文本处理器（38），连接到用于执行链接数据处理的文本处理器（38）的键盘和用于输出数据和文本字符信息的打印机和显示器（36,48,56） 。 该结构允许输入/输出端子（14）中的文本处理器（38）同时但是独立地模拟通常与主机中央处理单元相关联的显示器和打印机。

公开(公告)号：EP0067310A3

公开(公告)日：1984-02-15

申请号：EP82104116

申请日：1982-05-12

Applicant: International Business Machines Corporation

Inventor： Mueller, Mark Wayne ,  Parker, Thomas Shelton

IPC: H04L05/14 ,  H04L01/10

CPC classification number: H04L5/1423 ,  H04L1/0083

Abstract: A communication adapter circuit (10) is connected to a processor through processor I/0 interface buses (12, 14). Data and control signals are provided through the buses (12, 14) to a timer circuit (18), a programmable peripheral interface circuit (20), an asynchronous and bisynchronous control circuit (22) and an SDLC/HDLC control circuit (24). Each of the control circuits (22, 24) includes parallel-to-serial and serial-to-parallel conversion circuitry. A clock select circuit (32) operates in conjunction with the timer circuit (18) and the programmable peripheral interface circuit (20) to establish a data transmission rate for the data flow through the adapter circuit (10). From the control circuits (22, 24) the data is transmitted through a modem interface bus (44) to a dual modem switch (56). From the switch (56) the data is transmitted to either an EIA RS 232 interface circuit (60) to a conventional modem or through a bus (64) to an internal modem. A phase locked loop circuit in the control circuit (24) generates a data clock signal on a line (33) for operation of the adapter circuit (0) in the bisynchronous protocol with a non-clock-generating modem.

公开(公告)号：EP0067310A2

公开(公告)日：1982-12-22

申请号：EP82104116.7

申请日：1982-05-12

Applicant: International Business Machines Corporation

Inventor： Mueller, Mark Wayne ,  Parker, Thomas Shelton

IPC: H04L5/14 ,  H03M9/00

CPC classification number: H04L5/1423 ,  H04L1/0083

Abstract: A communication adapter circuit (10) is connected to a processor through processor I/0 interface buses (12, 14). Data and control signals are provided through the buses (12, 14) to a timer circuit (18), a programmable peripheral interface circuit (20), an asynchronous and bisynchronous control circuit (22) and an SDLC/HDLC control circuit (24). Each of the control circuits (22, 24) includes parallel-to-serial and serial-to-parallel conversion circuitry. A clock select circuit (32) operates in conjunction with the timer circuit (18) and the programmable peripheral interface circuit (20) to establish a data transmission rate for the data flow through the adapter circuit (10). From the control circuits (22, 24) the data is transmitted through a modem interface bus (44) to a dual modem switch (56). From the switch (56) the data is transmitted to either an EIA RS 232 interface circuit (60) to a conventional modem or through a bus (64) to an internal modem. A phase locked loop circuit in the control circuit (24) generates a data clock signal on a line (33) for operation of the adapter circuit (0) in the bisynchronous protocol with a non-clock-generating modem.

公开(公告)号：EP0067283A1

公开(公告)日：1982-12-22

申请号：EP82103174.7

申请日：1982-04-15

Applicant: International Business Machines Corporation

Inventor： Mueller, Mark Wayne ,  Parker, Thomas Shelton ,  Benignus, Douglas Marvin ,  Frye, James Lee

IPC: G06F13/00

CPC classification number: G06F13/385

Abstract: A communication adapter circuit (10) is connected to a processor through a data bus (12) and a control bus (14). Data and control signals are provided through the buses (12, 14) to a timer circuit (18), a programmable peripheral interface circuit (20), an asynchronous and bisynchronous control circuit (22) and an SDLC/HDLC control circuit (24). Each of the control circuits (22, 24) includes parallel-to-serial and serial-to-parallel conversion circuitry. A clock select circuit (32) operates in conjunction with the timer circuit (18) and the programmable peripheral interface circuit (20) to establish a data transmission rate for the data flow through the adapter circuit (10). From the control circuits (22, 24) the data is transmitted through a bi-directional serial line (44) to a dual modem switch (56). From the switch (56) the data is transmitted to either an interface circuit (60) to a conventional modem or through a line (64) to an internal modem.