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1.发明公开Buffer storage apparatus and data path concentrator incorporating this buffer storage apparatus 失效Pufferspeichervorrichtung und Datenwegkonzentrator mit dieser Pufferspeichervorrichtung。
公开(公告)号：EP0018518A1
公开(公告)日：1980-11-12
申请号：EP80101912.6
申请日：1980-04-10
CPC分类号： G06F5/16
摘要： The data bandwidth of bufferstorage apparatus comprising a set of buffers (A, B) is broadened by switching between the buffers when one of the buffers is empty and another one of the buffers has received a predetermined number of signals even though that data-receiving buffer is not yet full. With data transferred in blocks of data bytes, switching between buffers occurs on the address boundaries of the data blocks. Therefore, switching between buffers can occur at a plurality of points within the data-receiving one of the buffers. By using a plurality of such buffer storage apparatus to connect individual data burst units to a plural-port high-speed common unit, each data burst unit has greater access to the high speed common unit.
摘要翻译： 包括一组缓冲器（A，B）的缓冲存储装置的数据带宽通过在缓冲器中的一个为空并且缓冲器中的另一个已经接收到预定数量的信号时在缓冲器之间切换而变宽，即使该数据接收 缓冲区尚未满。 使用以数据字节为单位的数据传输，缓冲区之间的切换发生在数据块的地址边界上。 因此，缓冲器之间的切换可以发生在数据接收缓冲器之一内的多个点处。 通过使用多个这样的缓冲存储装置将各个数据突发单元连接到多端口高速公用单元，每个数据突发单元具有对高速公共单元的更大访问。
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公开(公告)号：EP0055369B1
公开(公告)日：1988-08-10
申请号：EP81108988.7
申请日：1981-10-27
CPC分类号： G06F13/124 , H04L29/00 , H04N1/32566
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3.发明公开Interface circuit and method for connecting a memory controller with a synchronous or an asynchronous bus system 失效用于将存储器控制器与同步或异步总线系统连接的接口电路和方法
公开(公告)号：EP0135879A3
公开(公告)日：1988-03-02
申请号：EP84110754
申请日：1984-09-10
IPC分类号： G06F13/16
CPC分类号： G06F13/4234
摘要： © An interface circuit for connecting a memory controller (208) to either a synchronous bus or an asynchronous bus. The interface circuit comprises switch means (197) for supplying a signal indicative of the type of bus and synchronizing means (198) for synchronizing memory access request signals with a local clock when the interface circuit is coupled to an asynchronous bus. An interface method of connecting memory circuits to either a synchronous bus or an asynchronous bus. The method comprises the generation of a mode signal indicative of the type of bus, and the synchronization of the memory access request signals with a local clock when the mode signals indicate an asynchronous bus.
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4.发明授权Buffer storage apparatus and data path concentrator incorporating this buffer storage apparatus 失效兼容本缓存存储设备的缓冲存储设备和数据路径集中器
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5.发明公开
公开(公告)号：EP0055369A2
公开(公告)日：1982-07-07
申请号：EP81108988.7
申请日：1981-10-27
CPC分类号： G06F13/124 , H04L29/00 , H04N1/32566
摘要： An electronic document distribution terminal includes a first adapter (12) coupled to data entry and document preparation means and a second adapter (15) coupled to data transmission means for communication, for example, with a similar terminal. Each of the adapters includes a processor for processing the data received from or for application to a coupled device. A peripheral processing memory (16) is employed to store data to be transferred between the adapters. This memory is under the control of a peripheral processing controller (10) whi allocates memory blocks to the adapters under the control of CPU 20. Thus each adapter operates as a stand-alone unit sharing a common memory with the CPU and peripheral processing controller performing only system control functions.
摘要翻译： 电子文件分配终端包括耦合到数据输入和文件准备装置的第一适配器（12）和耦合到例如类似终端进行通信的数据传输装置的第二适配器（15）。 每个适配器包括处理器，用于处理从耦合设备接收或应用于耦合设备的数据。 使用外围处理存储器（16）来存储要在适配器之间传送的数据。 该存储器在外围处理控制器（10）的控制下，外围处理控制器（10）在CPU 20的控制下向适配器分配存储块。因此，每个适配器作为独立单元操作，共享与CPU和外围处理控制器执行的公共存储器 只有系统控制功能。
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6.发明公开Selectable modification of medium in a printer system 失效AuswählbareModifikation eines einem Druckersystem中等。
公开(公告)号：EP0651318A2
公开(公告)日：1995-05-03
申请号：EP94480101.8
申请日：1994-10-07
发明人： Chen, Weilin (NMI) , Hohensee, Reinhard Heinrich , Shook, Frankie Sherwood , Marlin, James Warden , Nagda, Jagdish Mooljee , Stone, David Earl
IPC分类号： G06F3/12
CPC分类号： G06F3/1205 , G06F3/1264 , G06F3/1282
摘要： A computer-controlled printing system includes a host computer, an intelligent printer and an intelligent post printer processor. The print job is controlled by defining print data, printer control data and printer post processor control data in a print data stream from the host computer. The print data and printer control data are read at the intelligent printer. The intelligent printer executes the print control data to print the print data on a print medium. The printer also determines if there is post processor control data in the print data stream and, if so, sends the post processor control data from the printer to the intelligent post processor. The post processor reads the post processor control data, and executes the post processor control data to perform selected modification of the print medium. Selectable modifications of the print medium at the post processor include predetermined fixed printing of images, symbols or text, perforation of the print medium, cutting of the print medium, or user defined modifications of the print medium.
摘要翻译： 计算机控制的打印系统包括主机，智能打印机和智能后打印机处理器。 打印作业通过在主计算机的打印数据流中定义打印数据，打印机控制数据和打印机后处理器控制数据来控制。 在智能打印机上读取打印数据和打印机控制数据。 智能打印机执行打印控制数据以在打印介质上打印打印数据。 打印机还确定打印数据流中是否存在后处理器控制数据，如果是，则将后处理器控制数据从打印机发送到智能后处理器。 后处理器读取后处理器控制数据，并执行后处理器控制数据以执行打印介质的选择的修改。 后处理器上的打印介质的可选择的修改包括图像，符号或文本的预定固定打印，打印介质穿孔，打印介质的切割，或用户定义的打印介质的修改。
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7.发明授权Interface circuit and method for connecting a memory controller with a synchronous or an asynchronous bus system 失效用于将存储器控制器与同步或异步总线系统连接的接口电路和方法
公开(公告)号：EP0135879B1
公开(公告)日：1991-03-06
申请号：EP84110754.3
申请日：1984-09-10
IPC分类号： G06F13/16
CPC分类号： G06F13/4234
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8.发明公开Interface circuit and method for connecting a memory controller with a synchronous or an asynchronous bus system 失效接口电路和用于与一个同步或异步总线系统连接的存储器控制器的方法。
公开(公告)号：EP0135879A2
公开(公告)日：1985-04-03
申请号：EP84110754.3
申请日：1984-09-10
IPC分类号： G06F13/16
CPC分类号： G06F13/4234
摘要： © An interface circuit for connecting a memory controller (208) to either a synchronous bus or an asynchronous bus. The interface circuit comprises switch means (197) for supplying a signal indicative of the type of bus and synchronizing means (198) for synchronizing memory access request signals with a local clock when the interface circuit is coupled to an asynchronous bus.
An interface method of connecting memory circuits to either a synchronous bus or an asynchronous bus. The method comprises the generation of a mode signal indicative of the type of bus, and the synchronization of the memory access request signals with a local clock when the mode signals indicate an asynchronous bus.摘要翻译： 对于存储器控制器（208）连接到任何一个同步总线或异步总线上的接口电路。 该接口电路包括用于供应指示总线的类型的信号和同步用于与本地时钟当接口电路在异步总线耦合到同步存储器访问请求信号的装置（198）的开关装置（197）。 ... 存储电路连接到任何一个同步总线或异步总线上的接口方法。 该方法包括指示总线的类型的一个模式信号，并且所述存储器访问请求信号与本地时钟同步的产生。当模式信号指示异步总线。
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公开(公告)号：EP0055369A3
公开(公告)日：1984-08-15
申请号：EP81108988
申请日：1981-10-27
CPC分类号： G06F13/124 , H04L29/00 , H04N1/32566
摘要： An electronic document distribution terminal includes a first adapter (12) coupled to data entry and document preparation means and a second adapter (15) coupled to data transmission means for communication, for example, with a similar terminal. Each of the adapters includes a processor for processing the data received from or for application to a coupled device. A peripheral processing memory (16) is employed to store data to be transferred between the adapters. This memory is under the control of a peripheral processing controller (10) whi allocates memory blocks to the adapters under the control of CPU 20. Thus each adapter operates as a stand-alone unit sharing a common memory with the CPU and peripheral processing controller performing only system control functions.
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