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公开(公告)号：EP1384354A2
公开(公告)日：2004-01-28
申请号：EP02719909.0
申请日：2002-01-31
发明人： CALVIGNAC, Jean, Louis , GOETZINGER, William, John , HANDLOGTEN, Glen, Howard , HEDDES, Marco, C. , LOGAN, Joseph, Franklin , MIKOS, James, Francis , NORGAARD, David, Alan , VERPLANKEN, Fabrice
CPC分类号： H04L12/5601 , H04L2012/5636 , H04L2012/5679 , H04L2012/5685
摘要： A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.
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公开(公告)号：EP1384354B1
公开(公告)日：2012-07-25
申请号：EP02719909.0
申请日：2002-01-31
发明人： CALVIGNAC, Jean, Louis , GOETZINGER, William, John , HANDLOGTEN, Glen, Howard , HEDDES, Marco, C. , LOGAN, Joseph, Franklin , MIKOS, James, Francis , NORGAARD, David, Alan , VERPLANKEN, Fabrice
CPC分类号： H04L12/5601 , H04L2012/5636 , H04L2012/5679 , H04L2012/5685
摘要： A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.
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公开(公告)号：EP1380133B1
公开(公告)日：2005-03-23
申请号：EP02715591.0
申请日：2002-01-28
发明人： BASSO, Claude , CALVIGNAC, Jean, Louis , HEDDES, Marco , LOGAN, Joseph, Franklin , VERPLANKEN, Fabrice, Jean
CPC分类号： H04L49/901 , H04L12/1881 , H04L47/10 , H04L47/20 , H04L49/90
摘要： Multicast transmission on network processors is disclosed in order both to minimize multicast transmission memory requirements and to account for port performance discrepancies. Frame data for multicast transmission on a network processor is read into buffers to which are associated various control structures and a reference frame. The reference frame and the associated control structures permit multicast targets to be serviced without creating multiple copies of the frame. Furthermore this same reference frame and control structures allow buffers allocated for each multicast target to be returned to the free buffer queue without waiting until all multicast transmissions are complete.
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公开(公告)号：EP1362464A2
公开(公告)日：2003-11-19
申请号：EP02712095.5
申请日：2002-02-20
IPC分类号： H04L29/06
CPC分类号： H04L49/90 , H04L47/50 , H04L49/901
摘要： A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.
摘要翻译： 一种用于减少对存储器的访问次数以在帧控制块中获得期望的字段信息的方法和系统。 在本发明的一个实施例中，系统包括被配置为处理数据帧的处理器。 处理器可以包括被配置为接收和发送数据帧的数据流单元，其中每个数据帧可以具有相关联的帧控制块。 每个帧控制块包括第一和第二控制块。 处理器还可以包括耦合到数据流单元的第一存储器，其被配置为存储用于第一控制块的字段信息。 处理器还可以包括与数据流单元耦合的调度器，其中调度器被配置为调度由数据流单元接收的数据帧。 调度器可以包括被配置为存储第二控制块的字段信息的第二存储器。
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公开(公告)号：EP1208447A1
公开(公告)日：2002-05-29
申请号：EP00959157.9
申请日：2000-08-24
发明人： BASS, Brian, Mitchell , CALVIGNAC, Jean, Louis , HEDDES, Marco, C. , PATEL, Piyush, Chunilal , REVILLA, Juan, Guillermo , SIEGEL, Michael, Steven , VERPLANKEN, Fabrice, Jean
CPC分类号： H04Q11/0478 , H04L2012/5681
摘要： A network switch apparatus (10), components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate (10). The memory elements and interface processors together form a network processor (10) capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by a plurality of processors.
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6.发明授权STM-1 TO STM-64 SDH/SONET FRAMER WITH DATA MULTIPLEXING FROM A SERIES OF CONFIGURABLE I/O PORTS 有权STM-1至与一系列可配置的I / O端口中的数据复用STM-64 SDH / SONET成帧器
公开(公告)号：EP1423931B1
公开(公告)日：2006-07-26
申请号：EP02747299.2
申请日：2002-05-03
发明人： BARKER, Kenneth, James , CLAUBERG, Rolf , CALVIGNAC, Jean, Louis , HERKERSDORF, Andreas, Guenther , VERPLANKEN, Fabrice, Jean , WEBB, David, John
CPC分类号： H04J3/1611 , H04J3/0685 , H04J3/22 , H04J2203/0089
摘要： The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards.
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公开(公告)号：EP1273140A2
公开(公告)日：2003-01-08
申请号：EP01917224.6
申请日：2001-03-26
发明人： BASS, Brian, Mitchell , CALVIGNAC, Jean, Louis , HEDDES, Marco , SIEGEL, Michael, Steven , VERPLANKEN, Fabrice, Jean
CPC分类号： H04L12/5601 , H04L47/2408 , H04L47/50 , H04L47/527 , H04L47/564 , H04L2012/5636 , H04L2012/5649 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681
摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.
摘要翻译： 的系统和从向数据传输网络中的网络处理器中的优先顺序，其容纳几个不同级别的服务的移动信息单元的方法。 本发明包括一种用于从网络处理单元gemäß与信息单元的各个源相关联的存储的优先级的调度处理的信息单元（或帧）的出口的方法和系统。 在优选的实施方案重点包括低延迟服务，最小带宽，加权公平排队，并从持续了超过在较长时间内他的服务水平，防止用户的系统。 本发明包括不同的服务费率日历的多元化，以允许用户选择他期望的服务速度。 如果客户选择了服务高带宽，客户将被包含在一个日历所有这一切都被服务往往比如果客户选择了一个较低的带宽。
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公开(公告)号：EP1273140B1
公开(公告)日：2008-01-16
申请号：EP01917224.6
申请日：2001-03-26
发明人： BASS, Brian, Mitchell , CALVIGNAC, Jean, Louis , HEDDES, Marco , SIEGEL, Michael, Steven , VERPLANKEN, Fabrice, Jean
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L47/2408 , H04L47/50 , H04L47/527 , H04L47/564 , H04L2012/5636 , H04L2012/5649 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681
摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.
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公开(公告)号：EP1226501B1
公开(公告)日：2006-07-19
申请号：EP00959158.7
申请日：2000-08-24
发明人： BASS, Brian, Mitchell , CALVIGNAC, Jean, Louis , GALLO, Anthony, Matteo , HEDDES, Marco, C. c/o IBM United Kingdom Limited , RAO, Sridhar , SIEGEL, Michael, Steven , YOUNGMAN, Brian, Alan , VERPLANKEN, Fabrice, Jean
IPC分类号： G06F13/00 , G06F13/38 , G06F15/00 , G06F15/76 , G06F15/173
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
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公开(公告)号：EP1362465A2
公开(公告)日：2003-11-19
申请号：EP02712096.3
申请日：2002-02-20
IPC分类号： H04L29/06
CPC分类号： H04L49/3081 , G06F13/4243 , H04L2012/5681
摘要： A method and system for reducing memory accesses by inserting qualifiers in control blocks. In one embodiment, a system comprises a processor configured to process frames of data. The processor may comprise a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each control block, e.g., frame control block, buffer control block, may comprise one or more qualifier fields that comprise information unrelated to the current control block. Instead, qualifiers may comprise information related to an another control block. The last frame control block in a queue as well as the last buffer control block associated with a frame control block may comprise fields with no information thereby reducing memory accesses to access information in those fields.
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