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公开(公告)号：EP1208447A1
公开(公告)日：2002-05-29
申请号：EP00959157.9
申请日：2000-08-24
发明人： BASS, Brian, Mitchell , CALVIGNAC, Jean, Louis , HEDDES, Marco, C. , PATEL, Piyush, Chunilal , REVILLA, Juan, Guillermo , SIEGEL, Michael, Steven , VERPLANKEN, Fabrice, Jean
CPC分类号： H04Q11/0478 , H04L2012/5681
摘要： A network switch apparatus (10), components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate (10). The memory elements and interface processors together form a network processor (10) capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by a plurality of processors.
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公开(公告)号：EP1384354A2
公开(公告)日：2004-01-28
申请号：EP02719909.0
申请日：2002-01-31
发明人： CALVIGNAC, Jean, Louis , GOETZINGER, William, John , HANDLOGTEN, Glen, Howard , HEDDES, Marco, C. , LOGAN, Joseph, Franklin , MIKOS, James, Francis , NORGAARD, David, Alan , VERPLANKEN, Fabrice
CPC分类号： H04L12/5601 , H04L2012/5636 , H04L2012/5679 , H04L2012/5685
摘要： A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.
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公开(公告)号：EP1384354B1
公开(公告)日：2012-07-25
申请号：EP02719909.0
申请日：2002-01-31
发明人： CALVIGNAC, Jean, Louis , GOETZINGER, William, John , HANDLOGTEN, Glen, Howard , HEDDES, Marco, C. , LOGAN, Joseph, Franklin , MIKOS, James, Francis , NORGAARD, David, Alan , VERPLANKEN, Fabrice
CPC分类号： H04L12/5601 , H04L2012/5636 , H04L2012/5679 , H04L2012/5685
摘要： A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.
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公开(公告)号：EP1384354B8
公开(公告)日：2012-09-05
申请号：EP02719909.0
申请日：2002-01-31
发明人： CALVIGNAC, Jean, Louis , GOETZINGER, William, John , HANDLOGTEN, Glen, Howard , HEDDES, Marco, C. , LOGAN, Joseph, Franklin , MIKOS, James, Francis , NORGAARD, David, Alan , VERPLANKEN, Fabrice
CPC分类号： H04L12/5601 , H04L2012/5636 , H04L2012/5679 , H04L2012/5685
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公开(公告)号：EP1226509A1
公开(公告)日：2002-07-31
申请号：EP00957269.4
申请日：2000-08-24
发明人： BASS, Brian, Mitchell , CALVIGNAC, Jean-Louis , GALLO, Anthony, Matteo , HEDDES, Marco, C. , LEAVENS, Ross, Boyd , PATEL, Piyush, Chunilal , RINALDI, Mark, Anthony , SIEGEL, Michael, Steven , VERPLANKEN, Fabrice, Jean
IPC分类号： G06F15/00
CPC分类号： H04L49/602 , G06F15/80 , H04L49/351
摘要： A network processor (10) useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of an embedded processor complex (12) with a suite of peripherals (14-36 and 40), all formed on a common semiconductor substrate. The interface processors (16, 34) provide data path for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate, while storage of transiting data flow portions is provided by memory peripherals and interfaces to external memory elements.
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公开(公告)号：EP1208447B1
公开(公告)日：2007-02-21
申请号：EP00959157.9
申请日：2000-08-24
发明人： BASS, Brian, Mitchell , CALVIGNAC, Jean, Louis , HEDDES, Marco, C. , PATEL, Piyush, Chunilal , REVILLA, Juan, Guillermo , SIEGEL, Michael, Steven , VERPLANKEN, Fabrice, Jean
CPC分类号： H04Q11/0478 , H04L2012/5681
摘要： A network switch apparatus (10), components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate (10). The memory elements and interface processors together form a network processor (10) capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by a plurality of processors.
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公开(公告)号：EP1226501A1
公开(公告)日：2002-07-31
申请号：EP00959158.7
申请日：2000-08-24
发明人： BASS, Brian, Mitchell , CALVIGNAC, Jean, Louis , GALLO, Anthony, Matteo , HEDDES, Marco, C. , RAO, Sridhar , SIEGEL, Michael, Steven , YOUNGMAN, Brian, Alan , VERPLANKEN, Fabrice, Jean
IPC分类号： G06F13/00 , G06F13/38 , G06F15/00 , G06F15/76 , G06F15/173
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
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公开(公告)号：EP1208676A1
公开(公告)日：2002-05-29
申请号：EP00959159.5
申请日：2000-08-24
发明人： ALLEN, James, Jr. , BASS, Brian, Mitchell , CALVIGNAC, Jean, Louis , GAUR, Santosh, Prasad , HEDDES, Marco, C. , SIEGEL, Michael, Steven , VERPLANKEN, Fabrice, Jean
CPC分类号： H04Q3/002 , H04L45/742 , H04L49/254 , H04L49/351 , H04L49/354 , H04L49/602 , H04L2212/00 , H04Q3/5455 , H04Q2213/1302 , H04Q2213/13034 , H04Q2213/1304 , H04Q2213/13103 , H04Q2213/13104 , H04Q2213/13106 , H04Q2213/13107 , H04Q2213/13322
摘要： A network switching apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors (12) and a suite of peripheral elements formed on a semiconductor substrate (10). The interface processors (12) and peripherals together form a network processor capable of cooperating with other elements including an optional switch fabric device in executing instructions directing the flow of data in the network.
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