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    HIGH-PERFORMANCE CMOS SOI DEVICE ON HYBRID CRYSTAL-ORIENTED SUBSTRATES
    1.
    发明公开
    HIGH-PERFORMANCE CMOS SOI DEVICE ON HYBRID CRYSTAL-ORIENTED SUBSTRATES 审中-公开
    CMOS SOI元件上高性能的混合结晶取向SUBSTRATES

    公开(公告)号：EP1639637A1

    公开(公告)日：2006-03-29

    申请号：EP04741667.2

    申请日：2004-05-27

    申请人： International Business Machines Corporation ,  Compagnie IBM France

    发明人： DORIS, Bruce ,  GUARINI, Kathryn ,  LEONG, MeiKei ,  NARASIMHA, Shreesh ,  RIM, Kern ,  SLEIGHT, Jeffrey, W. ,  YANG, Min

    IPC分类号： H01L21/8238 ,  H01L21/84

    CPC分类号： H01L21/76275 ,  H01L21/823807 ,  H01L21/84

    摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material isregrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on theregrown material.

    FIN AND FINFET FORMATION BY ANGLED ION IMPLANTATION
    3.
    发明公开
    FIN AND FINFET FORMATION BY ANGLED ION IMPLANTATION 审中-公开
    FIN和教育的FinFET BY倾斜离子注入

    公开(公告)号：EP2396813A1

    公开(公告)日：2011-12-21

    申请号：EP10701234.6

    申请日：2010-01-22

    申请人： International Business Machines Corporation

    发明人： DORIS, Bruce ,  CHENG, Kangguo ,  WANG, Geng

    IPC分类号： H01L21/336 ,  H01L21/033

    摘要： A semiconductor device is formed by providing a substrate and forming a semiconductor-containing layer atop the substrate. A mask having a plurality of openings is then formed atop the semiconductor-containing layer, wherein adjacent openings of the plurality of openings of the mask are separated by a minimum feature dimension. Thereafter, an angled ion implantation is performed to introduce dopants to a first portion of the semiconductor-containing layer, wherein a remaining portion that is substantially free of dopants is present beneath the mask. The first portion of the semiconductor-containing layer containing the dopants is removed selective to the remaining portion of semiconductor-containing layer that is substantially free of the dopants to provide a pattern of sublithographic dimension, and the pattern is transferred into the substrate to provide a fin structure of sublithographic dimension.

    HIGHLY MANUFACTURABLE SRAM CELLS IN SUBSTRATES WITH HYBRID CRYSTAL ORIENTATION
    5.
    发明公开
    HIGHLY MANUFACTURABLE SRAM CELLS IN SUBSTRATES WITH HYBRID CRYSTAL ORIENTATION 有权
    HOCHPRODUZIERBARE在基底板混合杂交中的SRAM-ZELLEN

    公开(公告)号：EP1946375A1

    公开(公告)日：2008-07-23

    申请号：EP06777968.6

    申请日：2006-07-25

    申请人： International Business Machines Corporation

    发明人： DORIS, Bruce ,  COSTRINI, Gregory ,  GLUSCHENKOV, Oleg ,  LEONG, Meikei ,  SEONG, Nakgeuon

    IPC分类号： H01L27/11 ,  H01L21/8244

    CPC分类号： H01L27/1104 ,  H01L27/11 ,  Y10S257/903 ,  Y10S438/973

    摘要： The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.

    摘要翻译： 本发明涉及一种半导体器件结构，其包括形成在衬底中的至少一个SRAM单元。 这样的SRAM单元包括两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。 下拉晶体管和栅极晶体管在沟道宽度上基本相似，并且具有基本相似的源极 - 漏极掺杂浓度，而SRAM单元的β比率至少为1.5。 衬底优选地包括具有两个分离的区域集合的混合衬底，而这两组区域中的载流子迁移率差异至少约1.5。 更优选地，SRAM单元的下拉晶体管形成在一组区域中，并且栅极晶体管形成在另一组区域中，使得下拉晶体管中的电流大于 传输栅晶体管。