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    Self-referenced TAS-MRAM cell that can be read with reduced power consumption
    6.
    发明授权
    Self-referenced TAS-MRAM cell that can be read with reduced power consumption 有权

    公开(公告)号：EP2775480B1

    公开(公告)日：2018-11-14

    申请号：EP13290046.5

    申请日：2013-03-07

    申请人： Crocus Technology S.A.

    发明人： Stainer, Quentin

    IPC分类号： G11C11/16 ,  H01L43/02 ,  H01L43/08

    CPC分类号： G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/02 ,  H01L43/08

    摘要： Self-referenced magnetic random access memory (MRAM) cell (1) comprising a magnetic tunnel junction (2) including a sense layer (21); a storage layer (23) having a storage magnetization (230); a tunnel barrier layer (22) comprised between the sense and the storage layers (21, 23); and an antiferromagnetic layer (24) exchange-coupling the storage layer (23) such that the storage magnetization (230) can be pinned when the antiferromagnetic layer (24) is below a critical temperature and freely varied when the antiferromagnetic layer (24) is heated at or above the critical temperature; said sense layer (21) comprising a first sense layer (211) having a first sense magnetization (213), a second sense layer (212) having a second sense magnetization (214) and spacer layer (215) between the first and second sense layers (211, 212). The MRAM cell can be read with low power consumption.

    MEMORY CELLS, SEMICONDUCTOR DEVICE STRUCTURES, MEMORY SYSTEMS, AND METHODS OF FABRICATION
    7.
    发明授权
    MEMORY CELLS, SEMICONDUCTOR DEVICE STRUCTURES, MEMORY SYSTEMS, AND METHODS OF FABRICATION 有权

    公开(公告)号：EP2862172B1

    公开(公告)日：2018-10-24

    申请号：EP13807860.5

    申请日：2013-06-06

    申请人： Micron Technology, Inc.

    发明人： KULA, Witold ,  SANDHU, Gurtej S. ,  KRAMER, Stephen J.

    IPC分类号： H01L43/08 ,  H01L43/12 ,  H01L43/02

    CPC分类号： H01L43/08 ,  G11C11/161 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

    摘要： Methods of forming magnetic memory cells are disclosed. Magnetic and non-magnetic materials are formed into a primal precursor structure in an initial stress state of essentially no strain, compressive strain, or tensile strain. A stress-compensating material, e.g., a non-sacrificial, conductive material, is formed to be disposed on the primal precursor structure to form a stress-compensated precursor structure in a net beneficial stress state. Thereafter, the stress-compensated precursor structure may be patterned to form a cell core of a memory cell. The net beneficial stress state of the stress-compensated precursor structure lends to formation of one or more magnetic regions, in the cell core, exhibiting a vertical magnetic orientation without deteriorating a magnetic strength of the one or more magnetic regions. Also disclosed are memory cells, memory cell structures, semiconductor device structures, and spin torque transfer magnetic random access memory (STT-MRAM) systems.

    AN MRAM DEVICE AND ITS MANUFACTURING METHOD
    8.
    发明公开
    AN MRAM DEVICE AND ITS MANUFACTURING METHOD 审中-公开

    公开(公告)号：EP3367439A1

    公开(公告)日：2018-08-29

    申请号：EP17157919.6

    申请日：2017-02-24

    申请人： IMEC vzw ,  Katholieke Universiteit Leuven

    发明人： RAGHAVAN, Praveen ,  CROTTI, Davide Francesco ,  APPELTANS, Raf

    IPC分类号： H01L27/22

    CPC分类号： H01L43/02 ,  G11C5/06 ,  G11C11/161 ,  G11C2211/5615 ,  H01L27/228 ,  H01L43/12

    摘要： Disclosed is a device, comprising:
    a first interconnection level (110) including a first dielectric layer (112) and a first set of conductive paths (111) arranged in the first dielectric layer,
    a second interconnection level (120) arranged on the first connection level and including a second dielectric layer (122) and a second set of conductive paths (121) arranged in the second dielectric layer,
    a third interconnection level (130) arranged on the second interconnection level and including a third dielectric layer (132) and a third set of conductive paths (131) arranged in the third dielectric layer,
    a magnetic tunnel junction, MTJ, device (140) including a bottom layer (142), a top layer (146) and an MTJ structure (144) arranged between the bottom layer and the top layer, wherein the bottom layer is connected to a bottom layer contact portion (116) of the first set of conductive paths and the top layer is connected to a top layer contact portion (135) of the second or third set of conductive paths, and
    a multi-level via (150) extending through the second dielectric layer and the third dielectric layer, between a first via contact portion (118) of the first set of conductive paths and a second via contact portion (138) of the third set of conductive paths, wherein a height of the MTJ device corresponds to, or is less than, a height of the multi-level via.