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    Process or forming MOS-gated devices having self-aligned trenches
    1.
    发明公开
    Process or forming MOS-gated devices having self-aligned trenches 审中-公开
    一种用于与MOS栅极器件和自对准沟槽的制造过程

    公开(公告)号：EP1052690A3

    公开(公告)日：2003-12-03

    申请号：EP00108965.5

    申请日：2000-04-27

    申请人： Intersil Corporation

    发明人： Grebs, Thomas

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7802 ,  H01L29/41766 ,  H01L29/7813

    摘要： A process for forming an MOS-gated device having sell-aligned trenches, a screen oxide layer is formed on an upper layer of a semiconductor substrate, and a nitride layer is formed on the screen oxide layer. Using a well mask, the nitride layer is patterned and etched to define a well region in the upper layer, and ions of a first conduction type are diffused into the masked upper layer to form the well region. Ions of a second, opposite conduction type are implanted into the well region of the masked upper layer to form a source region extending to a selected depth that defines a source-well junction. The well mask is removed, exposing the portion of the nitride layer previously underlying the mask. An oxide insulating layer providing a hard mask is formed overlying the well and source regions in the upper layer. The remaining portions of the nitride layer and the screen oxide layer underlying it, which had been protected by the well mask, are removed, exposing the portion of the substrate not masked by the oxide insulating layer. The portion of the substrate thus exposed is etched to form a gate trench extending through the substrate to a selected depth beneath the well region. Sidewalls and a floor of an insulator are formed in the gate trench, which is filled with a semiconductor. The semiconductor in the trench is planarized to be substantially coplanar with the upper surface of the oxide insulating layer. An interlevel dielectric layer is formed on the planarized gate trench semiconductor and the upper surface of the oxide insulating layer.

    Process for forming vertical semiconductor device having increased source contact area
    3.
    发明公开
    Process for forming vertical semiconductor device having increased source contact area 审中-公开
    一种用于制造垂直半导体器件的方法具有增加的源极接触区

    公开(公告)号：EP1067596A2

    公开(公告)日：2001-01-10

    申请号：EP00114438.5

    申请日：2000-07-05

    申请人： Intersil Corporation

    发明人： Grebs, Thomas ,  Trost, Jason

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7802 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/6634 ,  H01L29/665 ,  H01L29/6656

    摘要： A process for forming a vertical semiconductor device having increased source contact area comprises forming on a silicon substrate a gate that comprises a layer of polysilicon deposited on a layer of oxide, and implanting and driving a dopant of a first conductivity type into the substrate to form a well region. A dopant of a second conductivity type is implanted and driven into the well region, to form a shallow source region in the well region, and a first layer of oxide is deposited over the gate and over the source and well regions in the substrate The first layer of oxide is etched to form a first spacer of oxide on the substrate adjacent the gate. A thin layer of nitride is deposited over the gate and over the source region, and a second layer of oxide is deposited over the thin nitride layer. The second layer of oxide is etched to form a second spacer of oxide that is separated from the first oxide spacer and the substrate by the thin nitride layer. Using the oxide and nitride spacers as a mask, the polysilicon layer in the gate and the source region in the substrate are selectively etched to remove the thin nitride layer from the gate and substrate, a portion of the gate polysilicon layer, and a portion of the source region, to forming in the source region a recessed portion that comprises substantially vertical and horizontal surfaces. A dopant of a first conductivity type is implanted and driven into the recessed portion of the source region, to form a shallow emitter region in the well region underlying the recessed portion of the source region. The second oxide spacer and the thin nitride layer separating it from the first oxide spacer are removed by etching, and a layer of conductive material is deposited on the remaining polysilicon layer and on the source region, whose recessed portion provides increased contact area with the conductive material.

    Process or forming MOS-gated devices having self-aligned trenches
    4.
    发明公开
    Process or forming MOS-gated devices having self-aligned trenches 审中-公开
    维也纳自治大学

    公开(公告)号：EP1052690A2

    公开(公告)日：2000-11-15

    申请号：EP00108965.5

    申请日：2000-04-27

    申请人： Intersil Corporation

    发明人： Grebs, Thomas

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7802 ,  H01L29/41766 ,  H01L29/7813

    摘要： A process for forming an MOS-gated device having sell-aligned trenches, a screen oxide layer is formed on an upper layer of a semiconductor substrate, and a nitride layer is formed on the screen oxide layer. Using a well mask, the nitride layer is patterned and etched to define a well region in the upper layer, and ions of a first conduction type are diffused into the masked upper layer to form the well region. Ions of a second, opposite conduction type are implanted into the well region of the masked upper layer to form a source region extending to a selected depth that defines a source-well junction. The well mask is removed, exposing the portion of the nitride layer previously underlying the mask. An oxide insulating layer providing a hard mask is formed overlying the well and source regions in the upper layer. The remaining portions of the nitride layer and the screen oxide layer underlying it, which had been protected by the well mask, are removed, exposing the portion of the substrate not masked by the oxide insulating layer.
    The portion of the substrate thus exposed is etched to form a gate trench extending through the substrate to a selected depth beneath the well region. Sidewalls and a floor of an insulator are formed in the gate trench, which is filled with a semiconductor. The semiconductor in the trench is planarized to be substantially coplanar with the upper surface of the oxide insulating layer. An interlevel dielectric layer is formed on the planarized gate trench semiconductor and the upper surface of the oxide insulating layer.

    摘要翻译： 在半导体衬底的上层形成用于形成具有销售对准沟槽的MOS门控器件，屏蔽氧化物层的工艺，并且在该氧化物层上形成氮化物层。 使用阱掩模，对氮化物层进行图案化和蚀刻以在上层中限定阱区，并且第一导电类型的离子扩散到掩蔽的上层中以形成阱区。 第二种相反导电类型的离子注入到被掩蔽的上层的阱区中，以形成延伸到限定源 - 阱结的选定深度的源区。 去除阱掩模，暴露先前在掩模下方的氮化物层的部分。 提供硬掩模的氧化物绝缘层形成在上层的阱和源极区域上。 已经被阱掩模保护的氮化物层及其下面的氧化屏层的其余部分被去除，暴露出未被氧化物绝缘层掩蔽的衬底部分。 蚀刻如此暴露的衬底的部分，以形成延伸穿过衬底的栅极沟槽到阱区下方的选定深度。 在栅极沟槽中形成侧壁和绝缘体的底板，其中填充有半导体。 沟槽中的半导体被平坦化以与氧化物绝缘层的上表面基本上共面。 在平坦化的栅极沟槽半导体和氧化物绝缘层的上表面上形成层间电介质层。

    Process for forming vertical semiconductor device having increased source contact area
    5.
    发明公开
    Process for forming vertical semiconductor device having increased source contact area 审中-公开
    一种用于制造垂直半导体器件的方法具有增加的源极接触区

    公开(公告)号：EP1067596A3

    公开(公告)日：2003-05-28

    申请号：EP00114438.5

    申请日：2000-07-05

    申请人： Intersil Corporation

    发明人： Grebs, Thomas ,  Trost, Jason

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7802 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/6634 ,  H01L29/665 ,  H01L29/6656

    摘要： A process for forming a vertical semiconductor device having increased source contact area comprises forming on a silicon substrate a gate that comprises a layer of polysilicon deposited on a layer of oxide, and implanting and driving a dopant of a first conductivity type into the substrate to form a well region. A dopant of a second conductivity type is implanted and driven into the well region, to form a shallow source region in the well region, and a first layer of oxide is deposited over the gate and over the source and well regions in the substrate The first layer of oxide is etched to form a first spacer of oxide on the substrate adjacent the gate. A thin layer of nitride is deposited over the gate and over the source region, and a second layer of oxide is deposited over the thin nitride layer. The second layer of oxide is etched to form a second spacer of oxide that is separated from the first oxide spacer and the substrate by the thin nitride layer. Using the oxide and nitride spacers as a mask, the polysilicon layer in the gate and the source region in the substrate are selectively etched to remove the thin nitride layer from the gate and substrate, a portion of the gate polysilicon layer, and a portion of the source region, to forming in the source region a recessed portion that comprises substantially vertical and horizontal surfaces. A dopant of a first conductivity type is implanted and driven into the recessed portion of the source region, to form a shallow emitter region in the well region underlying the recessed portion of the source region. The second oxide spacer and the thin nitride layer separating it from the first oxide spacer are removed by etching, and a layer of conductive material is deposited on the remaining polysilicon layer and on the source region, whose recessed portion provides increased contact area with the conductive material.

    摘要翻译： 一种用于形成垂直半导体器件的工艺具有增加的源极接触区域包括：形成在硅衬底的栅极并包括沉积氧化物的层上，多晶硅层中注入和驱动第一导电类型的掺杂剂注入到衬底以形成 井区。 的第二导电类型的掺杂剂注入和驱入阱区，以形成在所述阱区域中的浅源极区，和氧化物的第一层在所述基板的第一沉积在栅极和在源和阱区 氧化物层进行蚀刻，以形成氧化物对邻近栅极的基片的第一间隔物。 氮化物的薄层沉积在栅极和在所述源极区域，和氧化物的第二层沉积在该薄氮化物层。 氧化物的第二层被蚀刻以形成氧化物的第二间隔物并从所述第一氧化物间隔物和由薄氮化物层的衬底分离。 使用氧化物和氮化物间隔物作为掩膜，在栅极的多晶硅层和在基板上的源极区域被选择性地蚀刻，以从栅极和衬底，栅多晶硅层的一部分，且一部分移除薄氮化物层 源极区，在一个凹部确实包括基本上垂直和水平表面的源极区中形成。 第一导电类型的掺杂剂注入和驱入源极区域的凹部，以形成在所述阱区的源极区的凹部之下的浅结发射极区域。 第二氧化物间隔物和薄氮化物层从所述第一氧化物间隔分离而通过蚀刻去除，和导电材料的层沉积在剩余的多晶硅层上，并在源极区，谁的凹部提供与导电接触面积增加 材料。