公开(公告)号：EP2634796B1

公开(公告)日：2020-04-08

申请号：EP12189403.4

申请日：2012-10-22

申请人： J-Devices Corporation

发明人： Sawachi, Shigenori ,  Yamagata, Osamu ,  Inoue, Hiroshi ,  Itakura, Satoru ,  Chikai, Tomoshige ,  Hori, Masahiko ,  Katsumata, Akio

IPC分类号： H01L23/538 ,  H01L21/98

公开(公告)号：EP2634796A3

公开(公告)日：2015-03-25

申请号：EP12189403.4

申请日：2012-10-22

申请人： J-Devices Corporation

发明人： Sawachi, Shigenori ,  Yamagata, Osamu ,  Inoue, Hiroshi ,  Itakura, Satoru ,  Chikai, Tomoshige ,  Hori, Masahiko ,  Katsumata, Akio

IPC分类号： H01L23/538 ,  H01L21/98

摘要： A semiconductor device, comprising: a semiconductor element; a support substrate (1); an insulating material layer (4) for sealing the semiconductor element (2a, 2b) and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer (4), with a part thereof being exposed on an external surface; and metal vias (9) provided in the insulating material layer (4) and electrically connected to the metal thin film wiring layer, wherein the semiconductor element (2a, 2b) is provided in a plurality, and the respective semiconductor elements (2a, 2b) are stacked via an insulating material (4) such that a circuit surface of each semiconductor element (2a, 2b) faces the metal thin film wiring layer, and electrode pads of each semiconductor element (2a) are exposed without being hidden by the semiconductor element (2b) stacked thereabove, and electrically connected to the metal thin film wiring layer. The semiconductor device can be manufactured in a smaller and thinner size and the number of manufacturing steps can be reduced by causing a plurality of semiconductor chips to be a vertically-stacked structure.

摘要翻译： 一种半导体器件，包括：半导体元件; 支撑基板（1）; 一个用于密封半导体元件（2a，2b）及其周边的绝缘材料层（4） 设置在绝缘材料层（4）中的金属薄膜布线层，其一部分暴露在外表面上; 和设置在所述绝缘材料层（4）中并与所述金属薄膜布线层电连接的金属过孔（9），其中所述半导体元件（2a，2b）设置为多个，并且各个半导体元件（2a，2b ）通过绝缘材料（4）堆叠，使得每个半导体元件（2a，2b）的电路表面面对金属薄膜布线层，并且每个半导体元件（2a）的电极焊盘被暴露而不被半导体隐藏 元件（2b）堆叠在其上面，并且电连接到金属薄膜布线层。 通过使多个半导体芯片成为垂直层叠结构，能够使半导体装置小型化，薄型化，并且能够减少制造工序。

公开(公告)号：EP2634796A2

公开(公告)日：2013-09-04

申请号：EP12189403.4

申请日：2012-10-22

申请人： J-Devices Corporation

发明人： Sawachi, Shigenori ,  Yamagata, Osamu ,  Inoue, Hiroshi ,  Itakura, Satoru ,  Chikai, Tomoshige ,  Hori, Masahiko ,  Katsumata, Akio

IPC分类号： H01L21/98 ,  H01L25/065

摘要： A semiconductor device, comprising: a semiconductor element; a support substrate (1); an insulating material layer (4) for sealing the semiconductor element (2a, 2b) and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer (4), with a part thereof being exposed on an external surface; and metal vias (9) provided in the insulating material layer (4) and electrically connected to the metal thin film wiring layer, wherein the semiconductor element (2a, 2b) is provided in a plurality, and the respective semiconductor elements (2a, 2b) are stacked via an insulating material (4) such that a circuit surface of each semiconductor element (2a, 2b) faces the metal thin film wiring layer, and electrode pads of each semiconductor element (2a) are exposed without being hidden by the semiconductor element (2b) stacked thereabove, and electrically connected to the metal thin film wiring layer. The semiconductor device can be manufactured in a smaller and thinner size and the number of manufacturing steps can be reduced by causing a plurality of semiconductor chips to be a vertically-stacked structure.

摘要翻译： 一种半导体器件，包括：半导体元件; 支撑基板（1）; 用于密封半导体元件（2a，2b）的绝缘材料层（4）及其周边; 设置在绝缘材料层（4）中的金属薄膜布线层，其一部分露出在外表面上; 以及设置在所述绝缘材料层（4）中并电连接到所述金属薄膜布线层的金属通孔（9），其中所述半导体元件（2a，2b）设置为多个，并且所述半导体元件（2a，2b） ）通过绝缘材料（4）堆叠，使得每个半导体元件（2a，2b）的电路表面面向金属薄膜布线层，并且每个半导体元件（2a）的电极焊盘暴露而不被半导体隐藏 元件（2b），并且与金属薄膜布线层电连接。 半导体器件可以制造成更小和更薄的尺寸，并且可以通过使多个半导体芯片成为垂直堆叠的结构来减少制造步骤的数量。