公开(公告)号：EP3979499A1

公开(公告)日：2022-04-06

申请号：EP20812785.2

申请日：2020-03-18

申请人： Japan Science and Technology Agency

发明人： SUGAHARA, Satoshi ,  KITAGATA, Daiki ,  YAMAMOTO, Shuichiro

IPC分类号： H03K3/356 ,  G11C14/00 ,  G11C11/412 ,  G11C11/417

摘要： Provided is an electronic circuit including a cell array including memory cells each including a bistable circuit that includes a first inverter circuit and a second inverter circuit, each of the first inverter circuit and the second inverter circuit having a first mode characterized by there being substantially no hysteresis in transfer characteristics and a second mode characterized by there being hysteresis in transfer characteristics, wherein each of the first inverter circuit and the second inverter circuit are configured to be switchable between the first mode and the second mode, an output node and an input node of the first inverter circuit being coupled to an input node and an output node of the second inverter circuit, respectively, and a control circuit configured to, after powering off one or more first memory cells that are not required to retain data among the memory cells, put the bistable circuits in remaining one or more second memory cells of the memory cells into the second mode, and supply a second power supply voltage, at which the bistable circuit in the second mode can retain data, to the bistable circuits in the one or more second memory cells while maintaining the second mode, the second power supply voltage being lower than a first power supply voltage that is supplied to the bistable circuit when data is read and/or written.