公开(公告)号：EP0173288A3

公开(公告)日：1986-07-30

申请号：EP85110704

申请日：1985-08-26

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Hara, Hiroyuki c/o Patent Division ,  Nakamura, Michinori c/o Patent Division ,  Sugimoto, Yasuhiro c/o Patent Division

IPC分类号： H03K19/092

CPC分类号： H03K19/017527 ,  H03K19/01707

摘要： A voltage level converting circuit includes first and second potential terminals (P1, P2) between which a power source voltage is applied, first and second terminals (IN1, IN2) for receiving an input signal and an inverted input signal, a differential amplifier (T1, T2, IS) including npn transistors (T1, T2) whose conduction states are controlled by the input signal and the inverted input signal, and an output circuit for generating an output logic signal corresponding to the output voltage of the differential amplifier (T1, T2, IS). The output circuit of this voltage level converting circuit has a current path connected in series between the first and second potential terminals (P1, P2) by way of a constant current source (M3), and includes a MOS transistor (M2) whose conduction state is controlled by the ouptut voltage of the differential amplifier (T1, T2, IS).