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公开(公告)号：EP0384429A2
公开(公告)日：1990-08-29
申请号：EP90103330.8
申请日：1990-02-21
发明人： Saeki, Yukihiro, c/o Intellectual Property Div. , Suzuki, Yasoji, c/o Intellectual Property Div.
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17704 , H03K19/1731
摘要： A programmable logic circuit for deriving a logic output of first and second signals includes a 2-input logic gate (2) for deriving a logic output of two signals. The 2-input logic gate (2) is constituted by connecting two 3-state circuits (1₁, 1₂) in a wired OR configuration. One (1₁) of the 3-state circuits includes a data input terminal, output control input terminal, and data output terminal, the output control input terminal receives an inverted signal ( B ) of the second signal, and the data output terminal is set to one of three states of "1", "0", and the high impedance. Likewise, the other 3-state circuit (1₂) includes a data input terminal, output control input terminal, and data output terminal, the output control input terminal receives the second signal (B), and the data output terminal is set to one of three states of "1", "0", and the high impedance. Each of the data input terminals of the 3-state circuits (1₁, 1₂) is supplied with a desired one of the first signal (A), an inverted signal ( A ) of the first signal, a "0" level signal, and a "1" level signal in a programmable fashion. Various logic gates can be realized by programming the supplying states of the four signals.
摘要翻译： 用于导出第一和第二信号的逻辑输出的可编程逻辑电路包括用于导出两个信号的逻辑输出的2-输入逻辑门（2）。 2输入逻辑门（2）是通过以线或配置连接两个三态电路（1 1，1 2）而构成的。 三态电路中的一个（1 1）包括数据输入端，输出控制输入端和数据输出端，输出控制输入端接收第二信号的反相信号（B），并设置数据输出端 到“1”，“0”和高阻抗三种状态中的一种。 类似地，另一个三态电路（1 2）包括数据输入端，输出控制输入端和数据输出端，输出控制输入端接收第二信号（B），数据输出端设置为 “1”，“0”和高阻抗三种状态。 给三态电路（1 1，1 2）的每个数据输入端提供第一信号（A），第一信号的反相信号（A），“0”电平信号和 以可编程方式的“1”电平信号。 通过编程四个信号的供应状态可以实现各种逻辑门。
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公开(公告)号：EP0384429A3
公开(公告)日：1990-12-05
申请号：EP90103330.8
申请日：1990-02-21
发明人： Saeki, Yukihiro, c/o Intellectual Property Div. , Suzuki, Yasoji, c/o Intellectual Property Div.
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17704 , H03K19/1731
摘要： A programmable logic circuit for deriving a logic output of first and second signals includes a 2-input logic gate (2) for deriving a logic output of two signals. The 2-input logic gate (2) is constituted by connecting two 3-state circuits (1₁, 1₂) in a wired OR configuration. One (1₁) of the 3-state circuits includes a data input terminal, output control input terminal, and data output terminal, the output control input terminal receives an inverted signal ( B ) of the second signal, and the data output terminal is set to one of three states of "1", "0", and the high impedance. Likewise, the other 3-state circuit (1₂) includes a data input terminal, output control input terminal, and data output terminal, the output control input terminal receives the second signal (B), and the data output terminal is set to one of three states of "1", "0", and the high impedance. Each of the data input terminals of the 3-state circuits (1₁, 1₂) is supplied with a desired one of the first signal (A), an inverted signal ( A ) of the first signal, a "0" level signal, and a "1" level signal in a programmable fashion. Various logic gates can be realized by programming the supplying states of the four signals.
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