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11 条记录 (耗时 0.016 秒)

    Semiconductor memory device and storage method thereof
    1.
    发明公开
    Semiconductor memory device and storage method thereof 有权
    半导体存储器装置及其存储方法

    公开(公告)号：EP1870902A3

    公开(公告)日：2008-05-14

    申请号：EP07016632.7

    申请日：1999-12-22

    申请人： Kabushiki Kaisha Toshiba

    发明人： Shibata, Noboru ,  Tanaka, Tomoharu

    IPC分类号： G11C11/56

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C2211/5621 ,  G11C2211/5642

    摘要： For a verify operation using potential Vbi', the data of a memory cell (M1 through M16) is preliminarily read by using potential Vai+1 and the state of the memory cell is stored in a latch circuit. Then, a verify/read operation is conducted by using potential Vbi'. If the state of the cell is higher than Ai+1, the outcome of the verify/read operation is forcibly brought down to a low level. Thus, only two latch circuits (LAT(A), LAT(B)) are required for storing an n-bit data, including one for storing the data to be written and one for preliminarily reading if the state of the cell is higher than Ai+1 or not and storing the outcome of the preliminary reading.

    Semiconductor memory having redundancy memory cells
    2.
    发明公开
    Semiconductor memory having redundancy memory cells 失效
    Halbleiterspeicher mit redundanten Speicherzellen

    公开(公告)号：EP0778528A2

    公开(公告)日：1997-06-11

    申请号：EP96119623.5

    申请日：1996-12-06

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Shibata, Noboru ,  Kato, Hideo ,  Mochikuzi, Yoshio ,  Ikeda, Takafumi

    IPC分类号： G06F11/20

    CPC分类号： G11C29/80 ,  G11C29/808

    摘要： A redundancy memory cell array (12A, 12B) is arranged at an end of a main memory cell array (11A, 11B) in the column direction. Common bit lines and common column lines are arranged on the main memory cell array (11A, 11B) and the redundancy memory cell array (12A, 12B). A disconnection circuit (13A, 13B) is arranged between the main memory cell array (11A, 11B) and the redundancy memory cell array (12A, 12B) for connecting or disconnecting bit lines or column lines. A column selection switch (15A, 15B) is arranged at an end of the redundancy memory cell array (12A, 12B). A redundancy circuit (14) disconnects bit lines or column lines by means of a disconnection circuit (13A, 13B) when an address signal specifies a defective address.

    摘要翻译： 冗余存储单元阵列（12A，12B）被布置在列方向上的主存储单元阵列（11A，11B）的一端。 公共位线和公共列线被布置在主存储单元阵列（11A，11B）和冗余存储单元阵列（12A，12B）上。 在主存储单元阵列（11A，11B）和用于连接或断开位线或列线的冗余存储单元阵列（12A，12B）之间布置有断开电路（13A，13B）。 列选择开关（15A，15B）布置在冗余存储单元阵列（12A，12B）的一端。 当地址信号指定缺陷地址时，冗余电路（14）借助于断开电路（13A，13B）断开位线或列线。

    Semiconductor memory device and storage method thereof
    4.
    发明公开
    Semiconductor memory device and storage method thereof 有权
    半导体存储器装置及其存储方法

    公开(公告)号：EP1870902A2

    公开(公告)日：2007-12-26

    申请号：EP07016632.7

    申请日：1999-12-22

    申请人： Kabushiki Kaisha Toshiba

    发明人： Shibata, Noboru ,  Tanaka, Tomoharu

    IPC分类号： G11C11/56

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C2211/5621 ,  G11C2211/5642

    摘要： For a verify operation using potential Vbi', the data of a memory cell (M1 through M16) is preliminarily read by using potential Vai+1 and the state of the memory cell is stored in a latch circuit. Then, a verify/read operation is conducted by using potential Vbi'. If the state of the cell is higher than Ai+1, the outcome of the verify/read operation is forcibly brought down to a low level. Thus, only two latch circuits (LAT(A), LAT(B)) are required for storing an n-bit data, including one for storing the data to be written and one for preliminarily reading if the state of the cell is higher than Ai+1 or not and storing the outcome of the preliminary reading.

    Semiconductor memory device and storage method thereof
    5.
    发明公开
    Semiconductor memory device and storage method thereof 有权
    Halbleiterspeichervorrichtung und Speicherverfahrendafür

    公开(公告)号：EP1677310A1

    公开(公告)日：2006-07-05

    申请号：EP06006714.7

    申请日：1999-12-22

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Shibata, Noboru ,  Tanaka, Tomoharu

    IPC分类号： G11C11/56

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C2211/5621 ,  G11C2211/5642

    摘要： For a verify operation using potential Vbi', the data of a memory cell (M1 through M16) is preliminarily read by using potential Vai+1 and the state of the memory cell is stored in a latch circuit. Then, a verify/read operation is conducted by using potential Vbi'. If the state of the cell is higher than Ai+1, the outcome of the verify/read operation is forcibly brought down to a low level. Thus, only two latch circuits (LAT(A), LAT(B)) are required for storing an n-bit data, including one for storing the data to be written and one for preliminarily reading if the state of the cell is higher than Ai+1 or not and storing the outcome of the preliminary reading.

    摘要翻译： 对于使用电位Vbi'的验证操作，通过使用电位Vai + 1预先读取存储单元（M1至M16）的数据，并将存储单元的状态存储在锁存电路中。 然后，通过使用电位Vbi'进行验证/读取操作。 如果单元的状态高于Ai + 1，则验证/读取操作的结果被强制降低到低水平。 因此，只需要两个锁存电路（LAT（A），LAT（B））来存储n位数据，包括用于存储要写入的数据的一个数据，并且如果该单元的状态高于 Ai + 1或不存储初步阅读的结果。

    Semiconductor memory device and storage method thereof
    10.
    发明公开
    Semiconductor memory device and storage method thereof 有权
    Halbleiterspeicheranordnung und deren Speicherverffrenren

    公开(公告)号：EP1014381A1

    公开(公告)日：2000-06-28

    申请号：EP99125530.8

    申请日：1999-12-22

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Shibata, Noboru ,  Tanaka, Tomoharu

    IPC分类号： G11C11/56

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C2211/5621 ,  G11C2211/5642

    摘要： For a verify operation using potential Vbi', the data of a memory cell (M1 through M16) is preliminarily read by using potential Vai+1 and the state of the memory cell is stored in a latch circuit. Then, a verify/read operation is conducted by using potential Vbi'. If the state of the cell is higher than Ai+1, the outcome of the verify/read operation is forcibly brought down to a low level. Thus, only two latch circuits (LAT(A), LAT(B)) are required for storing an n-bit data, including one for storing the data to be written and one for preliminarily reading if the state of the cell is higher than Ai+1 or not and storing the outcome of the preliminary reading.

    摘要翻译： 对于使用电位Vbi'的验证操作，通过使用电位Vai + 1预先读取存储单元（M1至M16）的数据，并将存储单元的状态存储在锁存电路中。 然后，通过使用电位Vbi'进行验证/读取操作。 如果单元的状态高于Ai + 1，则验证/读取操作的结果被强制降低到低水平。 因此，只需要两个锁存电路（LAT（A），LAT（B））来存储n位数据，包括用于存储要写入的数据的一个数据，并且如果该单元的状态高于 Ai + 1或不存储初步阅读的结果。