STORAGE SYSTEM AND WAFER
    1.
    发明公开

    公开(公告)号:EP4002128A1

    公开(公告)日:2022-05-25

    申请号:EP20886245.8

    申请日:2020-10-21

    IPC分类号: G06F12/00 G01R31/28 H01L21/66

    摘要: The present invention curbs degradation in communication reliability between a probe electrode and a pad electrode. A storage system of one embodiment is provided with: a wafer comprising a memory chip unit that includes a pad electrode having a first portion and a second portion that are electrically connected to one another, and comprising a memory cell array electrically connected to the pad electrode; and a prober that is capable of holding the wafer and that reads/writes to/from the memory cell array. The prober comprises: a probe card having a probe electrode allowing for contact with the pad electrode, and having a memory controller capable of writing/reading to/from the memory cell array via the probe electrode; and a movement mechanism for causing the probe card or the held wafer to move, in order to bring the pad electrode of the held wafer and the probe electrode into contact. The movement mechanism is capable of executing: a first operation for bringing the probe electrode into contact with the first portion of the pad electrode without coming into contact with the second portion; and a second operation for bringing the probe electrode into contact with the second portion of the pad electrode without coming into contact with the first portion

    STORAGE DEVICE AND STORAGE SYSTEM
    2.
    发明公开

    公开(公告)号:EP4060720A1

    公开(公告)日:2022-09-21

    申请号:EP19932226.4

    申请日:2019-11-15

    摘要: A storage device includes a prober, and a stocker capable of storing a plurality of semiconductor wafers each of which includes a plurality of nonvolatile memory dies. A controller in the prober writes first identification information and a first check code to a first semiconductor wafer conveyed from the stocker to a stage in the prober when a set of identification information and an check code having correct correspondence is not stored in the first semiconductor wafer, and acquires a first logical-to-physical address translation table associated with the identification information of the first semiconductor wafer from a host computer or the first semiconductor wafer when the set of the identification information and the check code having the correct correspondence is stored in the first semiconductor wafer.

    STORAGE SYSTEM
    3.
    发明公开
    STORAGE SYSTEM 审中-公开

    公开(公告)号:EP4318246A1

    公开(公告)日:2024-02-07

    申请号:EP21932893.7

    申请日:2021-03-23

    摘要: A storage system useful for processing large amounts of data is provided.
    When a wafer cassette to be accessed that includes a first semiconductor wafer is not connected to a slot of a host apparatus and is stored in a wafer cassette stocker, the host apparatus causes a wafer cassette transport device to transport the wafer cassette to be accessed, to the slot of the host apparatus, and to connect it thereto. When the wafer cassette to be accessed is not connected to the slot of the host apparatus and is not stored in the wafer cassette stocker, the host apparatus causes a wafer transport device to transport the first semiconductor wafer from a wafer stocker to a cassetter, causes the cassetter to accommodate the first semiconductor wafer in a cassette case and causes the wafer cassette transport device to transport a wafer cassette to be accessed including the first semiconductor wafer to the slot of the host apparatus, and to connect it thereto.

    WAFER AND PROBER
    4.
    发明公开
    WAFER AND PROBER 审中-公开

    公开(公告)号:EP4307342A1

    公开(公告)日:2024-01-17

    申请号:EP21930041.5

    申请日:2021-03-08

    IPC分类号: H01L21/02 H01L21/66

    摘要: According to one embodiment, a wafer (10) includes a substrate (11) including a first region (RA) and a second region (RB) that do not overlap each other; a first chip unit and a second chip unit (100) each arranged on the substrate; a first electrode (16A) and a second electrode (16B) each electrically connected to the first chip unit; and a third electrode (16A) and a fourth electrode (16B) each electrically connected to the second chip unit. The first electrode and the third electrode are arranged in the first region. The second electrode and the fourth electrode are arranged in the second region. The first region is independent of a region in which the first chip unit and the second chip unit are provided.