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公开(公告)号：EP1766908A1
公开(公告)日：2007-03-28
申请号：EP05772293.6
申请日：2005-06-30
发明人： WOLTHEK, Jelle Nico , WAARDENBURG, Cornelis Klaas , KWAKERNAAT, Cecilius Gerardus , BUTSELAAR, Stefan Gerhard Erich
CPC分类号： H04L25/0296 , H03F3/45991 , H03F2203/45538 , H03F2203/45588 , H03F2203/45616 , H04L25/0274
摘要： The invention relates to a receiver for a differential bus with a switch control logic (151), with two branches with resistive elements (7, 61...70, 8 and 5, 11...20, 6) and with switches (3, 80) for switching the resistive elements, in which the switch control logic sets the switches - in a first routine for determining the absolute level of signals on the bus by applying a common mode voltage to the bus, by comparing the voltage on a first resistive branch with a reference voltage, by selecting the correct switch settings, and by writing these settings to an internal storage device, - and in a second routine for minimizing the mismatch between the two resistive branches by applying a common mode voltage to the bus, by comparing the voltage of the second resistive branch with that of the already trimmed first resistive branch, by selecting the correct switch settings for the second branch, and by writing these settings to an internal storage device. The receiver therefore provides good balancing and common mode rejection.
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公开(公告)号：EP1766908B1
公开(公告)日：2008-04-16
申请号：EP05772293.6
申请日：2005-06-30
发明人： WOLTHEK, Jelle Nico , WAARDENBURG, Cornelis Klaas , KWAKERNAAT, Cecilius Gerardus , BUTSELAAR, Stefan Gerhard Erich
CPC分类号： H04L25/0296 , H03F3/45991 , H03F2203/45538 , H03F2203/45588 , H03F2203/45616 , H04L25/0274
摘要： The invention relates to a receiver for a differential bus with a switch control logic (151), with two branches with resistive elements (7, 61...70, 8 and 5, 11...20, 6) and with switches (3, 80) for switching the resistive elements, in which the switch control logic sets the switches - in a first routine for determining the absolute level of signals on the bus by applying a common mode voltage to the bus, by comparing the voltage on a first resistive branch with a reference voltage, by selecting the correct switch settings, and by writing these settings to an internal storage device, - and in a second routine for minimizing the mismatch between the two resistive branches by applying a common mode voltage to the bus, by comparing the voltage of the second resistive branch with that of the already trimmed first resistive branch, by selecting the correct switch settings for the second branch, and by writing these settings to an internal storage device. The receiver therefore provides good balancing and common mode rejection.
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