-
公开(公告)号：EP1500145A1
公开(公告)日：2005-01-26
申请号：EP03712503.6
申请日：2003-04-01
IPC分类号： H01L31/00
CPC分类号： H04L25/49
摘要： An electronic device has a data communication bus (200) mounted on a semiconductor substrate (120). The data communication bus (200) has a first conductor (102), a second conductor (104), a third conductor (106) and afourth conductor (108). The conductors have been reordered and the distances (l1, l2, l3) between two neighboring conductors have been recalculated on the basis of the correlation between the data-bits conveyed by the conductors of the data communication bus (200), e.g. the number of times that the two transitions on two conductors have a predetermined value out of the total number of transitions on that conductor pair. Consequently, a data communication bus (200) is obtained in which the power consumption resulting from the charging of the cross-coupling capacitance between two neighboring conductors is reduced.
-
公开(公告)号：EP1435005B1
公开(公告)日：2005-12-14
申请号：EP02733102.4
申请日：2002-05-30
发明人： KLEIHORST, Richard, P. , DENISSEN, Adrianus, J., M. , NIEUWLAND, Andre, K. , BENSCHOP, Nico, F.
IPC分类号： G01R31/3185
CPC分类号： G01R31/3193 , G01R31/31921
-
3.发明公开DEVICE FOR PARALLEL DATA PROCESSING AS WELL AS A CAMERA SYSTEM COMPRISING SUCH A DEVICE 审中-公开装置上使用这样的设备并行处理和摄像系统
公开(公告)号：EP1563405A2
公开(公告)日：2005-08-17
申请号：EP03775761.4
申请日：2003-11-06
IPC分类号： G06F15/80
CPC分类号： H04N5/335
摘要： The invention relates to a device for parallel data processing, a DSP. The device according to the invention comprises a processor matrix (100) in which processors (103) are arranged in rows (101) and columns (102). Furthermore, the device (100) comprises first and second external data ports (107, 108). The rows (101) arranged in a stepwise manner and the columns are arranged in a stepwise manner. The processors (103) have a first processor data port (104), which is connected with one of the first external data ports (107) by means of first essentially straight connection. The processors (103) further comprise a second processor data port (105), which is connected with one of the second external data ports (108) by means of an essentially straight second connection (110). The first connection (107) and the second connection (108) are oriented substantially orthogonal to each other. A problem associated with conventional DSPs is that the connections to and from the processors within the DSP take up large amounts of silicon area. By arranging both rows and columns of the DSP according to the invention in a stepwise manner the connections may be essentially straight, thus minimizing their lengths and thus the surface area occupied.
-
公开(公告)号：EP1435005A2
公开(公告)日：2004-07-07
申请号：EP02733102.4
申请日：2002-05-30
发明人： KLEIHORST, Richard, P. , DENISSEN, Adrianus, J., M. , NIEUWLAND, Andre, K. , BENSCHOP, Nico, F.
IPC分类号： G01R31/3185
CPC分类号： G01R31/3193 , G01R31/31921
摘要： The invention relates to a digital system (1) and the method for error detection thereof. The digital system (1) comprises, as it's main core, a Module under Test (110) included in a Digital Processing Unit (100) and a State Parity Generator (SPG) (300). The SPG (300) is an equivalent with respect to parity of the Module under Test (300). An equivalent with respect to parity is a combinatorial circuit that, when an imput vector is applied at the imput of both Module under Test (110) and SPG (300), the output of the SPG (300) generates at it's output the parity of the transfer function of the Module under Test (110). The SPG (300) generates also a warning signal W when an unused combination of the imput vector is detected, the warning signal being treated as the parity signal.
-
公开(公告)号：EP1110326A1
公开(公告)日：2001-06-27
申请号：EP00943931.6
申请日：2000-06-28
CPC分类号： H03M7/30 , H04N19/115 , H04N19/124 , H04N19/126 , H04N19/137 , H04N19/15 , H04N19/152 , H04N19/176 , H04N19/18 , H04N19/192 , H04N19/30 , H04N19/60 , Y10S707/99942
摘要： Disclosed is a method of compressing information for storage in a fixed size memory. The data items (D(k)) that constitute the information are divided into pieces (D(s,k)) of decreasing significance. For example, the DCT blocks of an image are hierarchically quantized (3). The memory (5) is organized in corresponding memory layers (501-504). Successive memory layers have a decreasing number of memory locations. Every time a data item is applied to the memory, its less significant data pieces will have to compete with corresponding data pieces of previously stored data items. Depending on its contribution to perceptual image quality, the applied data piece is stored or the stored data piece is kept. Links (511-513, 521-522) are stored in the memory to identify the path along which a data item is stored. Eventually, the image is automatically compressed so as to exactly fit in the memory.
-
公开(公告)号：EP1430408B1
公开(公告)日：2007-04-11
申请号：EP02765186.8
申请日：2002-09-03
发明人： NIEUWLAND, Andre, K. , KLEIHORST, Richard, P. , VAN DIJK, Victor, E., S. , SALTERS, Roel, H., W.
IPC分类号： G06F13/42
CPC分类号： G06F13/4213 , Y02D10/14 , Y02D10/151
摘要： The electronic device (10) has a data communication bus (12) consisting of a plurality of substantially parallel conductors (12a, 12b, 12c, 12d). A control circuit (14) controls the values driven onto the conductors (12a, 12b, 12c, 12d). Transition dependent delay elements (16a, 16b, 16c, 16d) are coupled between the control circuit (14) and the respective conductors (12a, 12b, 12c, 12d) to delay certain transitions on the data communication bus 12. In particular, one of the opposite transitions on neighboring conductors e.g. a first conductor (12a) and a second conductor (12b) is delayed, thus reducing the power required to charge the mutual capacitance between the first conductor (12a) and the second conductor (12b). Consequently, a data communication bus (12) with reduced power consumption is obtained.
-
公开(公告)号：EP1110326B1
公开(公告)日：2005-11-23
申请号：EP00943931.6
申请日：2000-06-28
CPC分类号： H03M7/30 , H04N19/115 , H04N19/124 , H04N19/126 , H04N19/137 , H04N19/15 , H04N19/152 , H04N19/176 , H04N19/18 , H04N19/192 , H04N19/30 , H04N19/60 , Y10S707/99942
-
公开(公告)号：EP1405184A2
公开(公告)日：2004-04-07
申请号：EP02738454.4
申请日：2002-06-20
IPC分类号： G06F9/46
CPC分类号： G06F5/12 , G06F9/52 , G06F2205/102
摘要： A data processing apparatus according to the invention comprises at least a first (1, 2) and a second processor (1, 3), which processors are capable of communicating data to each other by exchanging tokens via a buffer according to a synchronization protocol. The protocol maintains synchronization information comprising at least a first and a second synchronization counter (writec, readc), which are readable by both processors. At least the first processor (1, 2) is capable of modifying the first counter (writec), and at least the second processor (1, 3) is capable of modifying the second counter (readc). The protocol comprises at least a first command (claim) which when issued by a processor results in a verification whether a requested number of tokens is available to said processor, and a second command (release) which results in updating one of the synchronization counters to indicate that tokens are released for use by the other processor. At least one of the processors (1, 3) comprises a storage facility for locally storing an indication (Nc; writec', readc) of the amount of tokens available to that processor, wherein issuing the first command (claim) results in a verification of the number of tokens available to said processor on the basis of said indication. A negative outcome of the verification results in updating of this indication on the basis of at least one of the synchronization counters. Issuing the second command (release) by a processor results in updating the indication in accordance with the number of tokens released to the other processor.
-
9.发明公开ELECTRONIC DEVICE HAVING LOGIC CIRCUITRY AND METHOD FOR DESIGNING LOGIC CIRCUITRY 审中-公开与逻辑电路电子设备的方法在尾逻辑电路
公开(公告)号：EP1820273A2
公开(公告)日：2007-08-22
申请号：EP05825398.0
申请日：2005-11-28
IPC分类号： H03K19/007
CPC分类号： H03K19/00338 , H03K19/00392
摘要： An electronic device with logic circuitry (LC) is provided. The logic circuitry (LC) comprises at least one electronic unit (EU), in particular one logic gate with a first electronic component (ECl) for performing logic operations; and at least one second electronic component (EC2) for improving the soft-error sensitivity of the logic circuitry (LC). The first and the second electronic component (ECl, EC2) are implemented with substantially the same logical function. The second electronic component (EC2) is redundant. In addition, the inputs of the first and the second electronic component (ECl, E2) are coupled and the outputs of the first and the second electronic component (ECl, E2) are coupled, respectively.
-
公开(公告)号：EP1745377A2
公开(公告)日：2007-01-24
申请号：EP05733777.6
申请日：2005-04-26
IPC分类号： G06F11/00
CPC分类号： G06F11/1008 , G11C7/22 , G11C7/24 , G11C11/406 , G11C2211/4062
摘要： An electronic circuit has a data producing circuit (12), such as a matrix of memory cells. A capture circuit (14) has an input coupled to the data producing circuit (10) for capturing the data signals after allowing a selected part of the data producing circuit to drive the input of the capture circuit. An error detection circuit (15) detects errors in the captured data signals. In response to detection of an error in particular data signals, the error detection circuit causes recapture of the particular data signals, allowing the data producing circuit (10) to drive the data signals at the input of the capture circuit (14) during a second time interval until recapture, the second time interval having a longer duration than the first time interval. This makes it possible to select the duration of the first time interval allowing for average driving speed of circuit parts (e.g. memory cells), without using a duration designed to account for worst case driving speed that may occur due to spread. Errors caused by spread are corrected by rereading with an increased time interval for driving the input of the capture circuit. Preferably, the duration of the first time interval is regulated so that on average a predetermined error rate occurs.
-
-
-
-
-
-
-
-
-
搜索结果
12 条记录 (耗时 0.012 秒)
