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公开(公告)号：EP1430408B1
公开(公告)日：2007-04-11
申请号：EP02765186.8
申请日：2002-09-03
发明人： NIEUWLAND, Andre, K. , KLEIHORST, Richard, P. , VAN DIJK, Victor, E., S. , SALTERS, Roel, H., W.
IPC分类号： G06F13/42
CPC分类号： G06F13/4213 , Y02D10/14 , Y02D10/151
摘要： The electronic device (10) has a data communication bus (12) consisting of a plurality of substantially parallel conductors (12a, 12b, 12c, 12d). A control circuit (14) controls the values driven onto the conductors (12a, 12b, 12c, 12d). Transition dependent delay elements (16a, 16b, 16c, 16d) are coupled between the control circuit (14) and the respective conductors (12a, 12b, 12c, 12d) to delay certain transitions on the data communication bus 12. In particular, one of the opposite transitions on neighboring conductors e.g. a first conductor (12a) and a second conductor (12b) is delayed, thus reducing the power required to charge the mutual capacitance between the first conductor (12a) and the second conductor (12b). Consequently, a data communication bus (12) with reduced power consumption is obtained.
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公开(公告)号：EP1656616A2
公开(公告)日：2006-05-17
申请号：EP04744750.3
申请日：2004-08-05
IPC分类号： G06F13/40
CPC分类号： G06F13/4072 , Y02D10/14 , Y02D10/151
摘要： A decoder circuit, for example a dual-rail decoder, receives input signals ( 43 ) from the end of a communications bus (not shown). The parity is calculated over the data wires (D o , D 1 , D 2 , D 3 ) using exclusive OR gates ( 45, 47, and 49 ). The calculated data parity signal ( 51 ) is compared with a transmitted parity signal ( 53 ) (shown as "carry") in an exclusive OR gate ( 55 ). Rather than connecting the control signal ( 57 ) from the exclusive OR gate ( 55 ) directly to the multiplexers ( 590, 591, 592, 593 ), the control signal ( 57 ) is instead connected to a gating circuit ( 71 ). The gating circuit ( 71 ), for example a AND gate, receives the control signal ( 57 ) as a first input signal. The gating circuit ( 71 ) also receives a second input signal in the form of a gating control signal ( 73 ). The gating control signal ( 73 ) is delayed by a predetermined amount, for example corresponding to the worst case delay of the signals in the input data signals ( 43 ). Thus, the gating control signal ( 73 ) does not control the gating circuit until such time as all of the data signals are valid, ie until the last transition on the data signal ( 43 ) has occurred, thereby preventing glitches and reducing power consumption in the decoder circuit.
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公开(公告)号：EP1430408A1
公开(公告)日：2004-06-23
申请号：EP02765186.8
申请日：2002-09-03
发明人： NIEUWLAND, Andre, K. , KLEIHORST, Richard, P. , VAN DIJK, Victor, E., S. , SALTERS, Roel, H., W.
IPC分类号： G06F13/42
CPC分类号： G06F13/4213 , Y02D10/14 , Y02D10/151
摘要： The electronic device (10) has a data communication bus (12) consisting of a plurality of substantially parallel conductors (12a, 12b, 12c, 12d). A control circuit (14) controls the values driven onto the conductors (12a, 12b, 12c, 12d). Transition dependent delay elements (16a, 16b, 16c, 16d) are coupled between the control circuit (14) and the respective conductors (12a, 12b, 12c, 12d) to delay certain transitions on the data communication bus 12. In particular, one of the opposite transitions on neighboring conductors e.g. a first conductor (12a) and a second conductor (12b) is delayed, thus reducing the power required to charge the mutual capacitance between the first conductor (12a) and the second conductor (12b). Consequently, a data communication bus (12) with reduced power consumption is obtained.
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公开(公告)号：EP1540828A1
公开(公告)日：2005-06-15
申请号：EP03795107.6
申请日：2003-08-06
IPC分类号： H03M5/02
CPC分类号： H04L25/0266 , G01R31/318538 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a method for coding information in an electronic circuit and an electronic circuit for coding information, said circuit comprising at least two electrically coupled signal paths (X0, X1). The invention is based on the idea that cross-talk between two electrically coupled signal paths (X0, X1) can be utilized to perform logical computation. A signal is propagating on two signal paths (X0, X1) in the form of either rising or falling transitions. The relative delay between the transitions on the two paths (X0, X1) determines the logic value of the output signal (X) to be produced. If the signal on the first path (X0) propagates faster than the signal on the second path (X1), an output signal (X) having a first logic value is produced. If the signal on the second path (X1) propagates faster than the signal on the first path (X0), an output signal (X) having a second logic value is produced.
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公开(公告)号：EP1402637A1
公开(公告)日：2004-03-31
申请号：EP02735719.3
申请日：2002-06-04
IPC分类号： H03K5/13
CPC分类号： H03K5/131 , H03K5/15013
摘要： The invention relates to a controllable delay circuit (2) for delaying an electrical input signal (4) wherein the controllable delay circuit (2) is arranged for receiving an input signal (4) and at least one control signal (6), wherein, in use, the delay circuit (2) delays the input signal (4) by a delay for generating an output signal (8), wherein the delay is a function of the at least one control signal (6), wherein the delay circuit (2) comprises a first module (10) for generating a base signal (11) and at least one support signal (12) on the basis of the input signal (4) and the at least one control signal (6), wherein, in use, the phase and/or the amplitude of the at least one support signal (12) is controllable with respect to the phase and /or the amplitude of the base-signal (11) by means of the at least one control signal (6), wherein the delay circuit (2) also comprises a second module (14) connected to the first module (10), which second module (14) comprises a signal-conductor (16) and at least one support conductor (18), wherein the signal conductor (16) and the at least one support conductor extend (18), at least over a part of the conductors, essentially parallel to one another in one another's vicinity, wherein, in use, the first module (10) supplies the base signal (11) to a first end of the signal conductor (16) for generating an output-signal (8) at a second end of the signal conductor (16), and wherein, in use, the first module (10) supplies the at least one support signal (12) to the at least one support conductor (18).
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公开(公告)号：EP1500145A1
公开(公告)日：2005-01-26
申请号：EP03712503.6
申请日：2003-04-01
IPC分类号： H01L31/00
CPC分类号： H04L25/49
摘要： An electronic device has a data communication bus (200) mounted on a semiconductor substrate (120). The data communication bus (200) has a first conductor (102), a second conductor (104), a third conductor (106) and afourth conductor (108). The conductors have been reordered and the distances (l1, l2, l3) between two neighboring conductors have been recalculated on the basis of the correlation between the data-bits conveyed by the conductors of the data communication bus (200), e.g. the number of times that the two transitions on two conductors have a predetermined value out of the total number of transitions on that conductor pair. Consequently, a data communication bus (200) is obtained in which the power consumption resulting from the charging of the cross-coupling capacitance between two neighboring conductors is reduced.
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