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    APPLICATION SPECIFIC MODULES IN A PROGRAMMABLE LOGIC DEVICE
    1.
    发明授权
    APPLICATION SPECIFIC MODULES IN A PROGRAMMABLE LOGIC DEVICE 失效
    应用专用模块在可编程逻辑器件

    公开(公告)号：EP0734573B1

    公开(公告)日：2002-04-03

    申请号：EP95904802.6

    申请日：1994-12-13

    申请人： LATTICE SEMICONDUCTOR CORPORATION

    发明人： TSUI, Cyrus, Y. ,  SHANKAR, Kapil ,  CHAN, Albert, L.

    IPC分类号： G11C11/40 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/17744 ,  H03K19/1736 ,  H03K19/17704 ,  H03K19/17732

    摘要： A structure and a method provide a programmable logic device (200) including a number of generic logic blocks (203a-203l) or more application-specific block (203b). Such application-specific block implements a specific function, such as a register file or a memory array (420). In one embodiment, the application-specific block is programmable to be either one or more single-port memory array, a first-in-first-out (FIFO) memory, or a dual port memory array. In another embodiment, the application-specific block can be configured to be a register file, a number of counters, a number of timers, or a shift register. The application-specific block can be used in conjunction with programmable logic arrays for multiplexing input and output signals into and out of the application-specific block. Interconnectivity between the generic logic blocks and the application-specific blocks, using a global routing resource, integrates into a programmable logic device, functions otherwise difficult to implement using only generic logic blocks.

    PROGRAMMABLE INTERCONNECT STRUCTURE FOR LOGIC BLOCKS
    3.
    发明公开
    PROGRAMMABLE INTERCONNECT STRUCTURE FOR LOGIC BLOCKS 失效
    可编程连接结构的逻辑块。

    公开(公告)号：EP0583361A1

    公开(公告)日：1994-02-23

    申请号：EP92911404.0

    申请日：1992-05-06

    申请人： LATTICE SEMICONDUCTOR CORPORATION

    发明人： SHANKAR, Kapil

    IPC分类号： H03K19

    CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

    摘要： L'invention concerne une structure pour effectuer des connexions (X) programmables entre les bornes d'entrée (I0-I7) et de sortie (O0-07) de blocs (20, 21) logiques individuels dans un dispositif logique. Dans un mode de réalisation, chaque borne de sortie (O0-O7) est connectée de manière programmable à une seule borne d'entrée (I0-I7) de chaque bloc logique (20 et 21). Le même principe est suivi pour effectuer des connexions entre les broches d'entrée du dispositif et les bornes d'entrée des blocs logiques.

    APPLICATION SPECIFIC MODULES IN A PROGRAMMABLE LOGIC DEVICE
    4.
    发明公开
    APPLICATION SPECIFIC MODULES IN A PROGRAMMABLE LOGIC DEVICE 失效
    应用专用模块在可编程逻辑器件

    公开(公告)号：EP0734573A1

    公开(公告)日：1996-10-02

    申请号：EP95904802.0

    申请日：1994-12-13

    申请人： LATTICE SEMICONDUCTOR CORPORATION

    发明人： TSUI, Cyrus, Y. ,  SHANKAR, Kapil ,  CHAN, Albert, L.

    IPC分类号： G11C11 ,  H03K19

    CPC分类号： H03K19/17744 ,  H03K19/1736 ,  H03K19/17704 ,  H03K19/17732

    摘要： A structure and a method provide a programmable logic device (200) including a number of generic logic blocks (203a-203l) or more application-specific block (203b). Such application-specific block implements a specific function, such as a register file or a memory array (420). In one embodiment, the application-specific block is programmable to be either one or more single-port memory array, a first-in-first-out (FIFO) memory, or a dual port memory array. In another embodiment, the application-specific block can be configured to be a register file, a number of counters, a number of timers, or a shift register. The application-specific block can be used in conjunction with programmable logic arrays for multiplexing input and output signals into and out of the application-specific block. Interconnectivity between the generic logic blocks and the application-specific blocks, using a global routing resource, integrates into a programmable logic device, functions otherwise difficult to implement using only generic logic blocks.

    OUTPUT LOGIC MACROCELL WITH ENHANCED FUNCTIONAL CAPABILITIES
    5.
    发明公开
    OUTPUT LOGIC MACROCELL WITH ENHANCED FUNCTIONAL CAPABILITIES 失效
    输出和改进的功能可能性逻辑宏小区。

    公开(公告)号：EP0583371A1

    公开(公告)日：1994-02-23

    申请号：EP92911860.0

    申请日：1992-04-29

    申请人： LATTICE SEMICONDUCTOR CORPORATION

    发明人： SHEN, Ju ,  CHAN, Albert, L. ,  SHANKAR, Kapil ,  TSUI, Cyrus

    IPC分类号： H03K19

    CPC分类号： H03K19/1736

    摘要： Une macrocellule logique de sortie ("OLMC" 30a) contenant une porte OU exclusif (309a) est associée aux termes de produit (P) et autres sorties d'un bloc logique tel qu'un réseau logique programmable. La macrocellule logique de sortie (30a) est capable d'assurer de meilleures fonctions, y compris des portes OU exclusif en cascade, la répartition des fonctions, l'émulation des bascules T et JK, la synchronisation asynchrone, et la sélection de remise à l'état initial. De plus, un bloc logique est utilisé en tant que source d'une impulsion d'horloge asynchrone et est connecté au système de distribution d'horloge globale (320a) d'un dispositif tel qu'un dispositif logique programmable de haute densité.