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    Low-power and area-efficient scan cell for integrated circuit testing
    3.
    发明公开
    Low-power and area-efficient scan cell for integrated circuit testing 有权
    Niederstrom- und bereichswirksame-Scanzellefüreine integrierteSchaltungsprüfung

    公开(公告)号：EP2503347A1

    公开(公告)日：2012-09-26

    申请号：EP12160993.7

    申请日：2012-03-23

    申请人： LSI Corporation

    发明人： Tekumalla, Ramesh C ,  Kumar, Priyesh ,  Krishnamoorthy, Prakash ,  Madhani, Parag

    IPC分类号： G01R31/3185

    CPC分类号： G01R31/318541 ,  G01R31/318575

    摘要： An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, with the scan chain being configured to operate as a serial shift register in a scan shift mode of operation and to capture functional data from at least a portion of the additional circuitry in a functional mode of operation. At least a given one of the scan cells of the scan chain comprises output control circuitry which is configured to disable a functional data output of the scan cell in the scan shift mode of operation and to disable a scan output of the scan cell in the functional mode of operation.

    摘要翻译： 集成电路包括扫描测试电路和经受使用扫描测试电路的测试的附加电路。 扫描测试电路包括具有多个扫描单元的至少一个扫描链，其中扫描链被配置为以扫描移动模式运行作为串行移位寄存器，并从附加的至少一部分中捕获功能数据 功能运行模式的电路。 扫描链的至少一个扫描单元中的一个包括输出控制电路，其被配置为在扫描移动运行模式中禁用扫描单元的功能数据输出，并禁用功能中的扫描单元的扫描输出 操作模式。