公开(公告)号：EP3345187A1

公开(公告)日：2018-07-11

申请号：EP16842708.6

申请日：2016-08-26

申请人： Lattice Semiconductor Corporation

发明人： OMID-ZOHOOR, Farrokh Kia ,  BUI, Nguyen, Duc ,  LY, Binh

IPC分类号： G11C17/16 ,  G11C17/18

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L27/11206 ,  H01L27/11582 ,  H01L28/00

摘要： A non-volatile programmable bitcell has a read enable device with a source coupled with a bitline, an anti-fuse device with a gate coupled with a first write line, a drain coupled with a supply voltage and a source coupled with a drain of the read enable device. The bitcell has a fuse device coupled between a second write line and the drain of the read enable device. A magnitude of current flowing in the bitline, when the read enable device is enabled for reading, is dependent both on (1) a voltage level applied to the first write line and anti-fuse device state and on (2) a voltage level applied to the second write line and fuse device state. Usages include in a memory array, such as for FPGA configuration memory. The bitcell can be used as a multi-time programmable element, or to store multiple bit values.