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    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权
    Halbleiterbauelement

    公开(公告)号：EP2575137B1

    公开(公告)日：2017-01-04

    申请号：EP12186212.2

    申请日：2012-09-27

    申请人： PS4 Luxco S.a.r.l.

    发明人： Kondo, Chikara

    IPC分类号： G11C7/22 ,  G11C7/10 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4072

    CPC分类号： G11C11/4093 ,  G06F13/161 ,  G11C7/1045 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4063 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/14

    摘要： Disclosed herein is a semiconductor device that includes a command decoder activating a first mode register setting signal in response to a mode register setting command supplied from outside, a first latency shifter activating a second mode register setting signal after elapse of predetermined cycles of a clock signal since the first mode register setting signal is activated, and a mode register storing a mode signal supplied from outside in response to the second mode register setting signal.

    摘要翻译： 这里公开了一种半导体器件，其包括响应于从外部提供的模式寄存器设置命令来激活第一模式寄存器设置信号的命令解码器，在经过时钟信号的预定周期之后激活第二模式寄存器设置信号的第一等待时间移位器 由于第一模式寄存器设置信号被激活，并且模式寄存器响应于第二模式寄存器设置信号存储从外部提供的模式信号。

    METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS OPERATIONS
    7.
    发明授权
    METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS OPERATIONS 有权
    方法和装置线和SPLATENBETRIEB同步已

    公开(公告)号：EP1301927B1

    公开(公告)日：2012-06-27

    申请号：EP01951275.5

    申请日：2001-07-06

    申请人： Mosaid Technologies Incorporated

    发明人： DEMONE, Paul

    IPC分类号： G11C11/408 ,  G11C11/4076 ,  G11C7/22 ,  G11C8/18

    CPC分类号： G11C7/1072 ,  G11C7/08 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C2207/002 ,  G11C2207/065 ,  G11C2207/2281

    摘要： A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit lines pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated after the sense amplifier power supply circuit is enabled.