公开(公告)号：EP1267405A3

公开(公告)日：2004-11-24

申请号：EP01130716.2

申请日：2001-12-21

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Kishida, Takenobu ,  Tada, Shinya ,  Ikeda, Atsushi ,  Harada, Takeshi ,  Sugihara, Kohei

IPC分类号： H01L23/532

CPC分类号： H01L21/76843 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A barrier layer is formed on an insulating or conducting film provided on a semiconductor substrate, and an electrode or an interconnect made from a conducting film is formed on the barrier layer. The barrier layer includes a tantalum film having the β-crystal structure.

摘要翻译： 在设置于半导体衬底上的绝缘或导电膜上形成阻挡层，并且在阻挡层上形成由导电膜制成的电极或互连。 阻挡层包括具有β晶体结构的钽膜。

公开(公告)号：EP1385202A2

公开(公告)日：2004-01-28

申请号：EP03016803.3

申请日：2003-07-23

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Tarumi, Nobuaki ,  Ikeda, Atsushi ,  Kishida, Takenobu

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873

摘要： A lower barrier layer made of tantalum nitride (19) having a thickness of approximately 25nm is deposited by sputtering on an insulating film (17) inclusive of the sidewall surfaces and the bottom surfaces of a via hole (17a) and an upper-interconnect-forming groove (18a). The sputtering is performed under the conditions where approximately 10kW of DC source power is applied to a target. Thereafter, the DC source power is reduced to approximately 2kW, and approximately 200W of RF power is applied to a semiconductor substrate. Here, the lower barrier layer is subjected to a sputter-etching process employing argon gas at an etching amount of approximately 5nm, so that a part of the lower barrier layer deposited on the bottom surface of the via hole is at least partially deposited on the lower part of the sidewall surface of the via hole.

摘要翻译： 通过溅射将由氮化钽（19）制成的厚度约为25nm的下阻挡层沉积在绝缘膜（17）上，该绝缘膜（17）包括侧​​壁表面和通孔（17a）的底表面和上部互连 - 形成槽（18a）。 在将大约10kW的直流电源施加到目标的条件下进行溅射。 此后，DC源功率降低到约2kW，并且将大约200W的RF功率施加到半导体衬底。 这里，下蚀刻层用蚀刻量约5nm的氩气进行溅射蚀刻，使得沉积在通孔底面的下阻挡层的一部分至少部分沉积在 通孔的侧壁表面的下部。

公开(公告)号：EP1385202A3

公开(公告)日：2006-03-22

申请号：EP03016803.3

申请日：2003-07-23

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Tarumi, Nobuaki ,  Ikeda, Atsushi ,  Kishida, Takenobu

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873

摘要： A lower barrier layer made of tantalum nitride (19) having a thickness of approximately 25nm is deposited by sputtering on an insulating film (17) inclusive of the sidewall surfaces and the bottom surfaces of a via hole (17a) and an upper-interconnect-forming groove (18a). The sputtering is performed under the conditions where approximately 10kW of DC source power is applied to a target. Thereafter, the DC source power is reduced to approximately 2kW, and approximately 200W of RF power is applied to a semiconductor substrate. Here, the lower barrier layer is subjected to a sputter-etching process employing argon gas at an etching amount of approximately 5nm, so that a part of the lower barrier layer deposited on the bottom surface of the via hole is at least partially deposited on the lower part of the sidewall surface of the via hole.

公开(公告)号：EP1267405A2

公开(公告)日：2002-12-18

申请号：EP01130716.2

申请日：2001-12-21

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Kishida, Takenobu ,  Tada, Shinya ,  Ikeda, Atsushi ,  Harada, Takeshi ,  Sugihara, Kohei

IPC分类号： H01L23/532

CPC分类号： H01L21/76843 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A barrier layer is formed on an insulating or conducting film provided on a semiconductor substrate, and an electrode or an interconnect made from a conducting film is formed on the barrier layer. The barrier layer includes a tantalum film having the β-crystal structure.