公开(公告)号：EP4369386A1

公开(公告)日：2024-05-15

申请号：EP23208718.9

申请日：2023-11-09

申请人： STMicroelectronics S.r.l.

发明人： GUARINO, Lucrezia ,  MILANESI, Francesca ,  ZAFFERONI, Claudio

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/485

CPC分类号： H01L21/76849 ,  H01L21/76865 ,  H01L21/76831 ,  H01L21/7682 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02320130101 ,  H01L2224/0404220130101 ,  H01L2224/0501720130101 ,  H01L2224/0501120130101 ,  H01L2224/0502420130101 ,  H01L2224/0502620130101 ,  H01L2224/0554720130101 ,  H01L2224/0556220130101 ,  H01L2224/0556720130101 ,  H01L21/76843 ,  H01L23/53295 ,  H01L23/5283 ,  H01L21/76885

摘要： A semiconductor device has a conductive structure (201) on a conductive barrier layer (230, 302) that separates the conductive structure from a conductive layer (244) on which the conductive barrier layer is present. A gap or crevice (260; 330) extends along respective surfaces of the conductive structure and along respective surfaces of one or more insulating layers. The gap or crevice separates the respective surfaces of the one or more insulating layers from the respective surfaces of the conductive structure. The gap or crevice provides clearance in which the conductive structure may expand into when exposed to changes in temperature. For example, when coupling a wire bond to the conductive structure, the conductive structure may increase in temperature and expand into the gap or crevice. However, even in the expanded state, respective surfaces of the conductive structure do not physically contact the respective surfaces of the one or more insulating layers.

公开(公告)号：EP3084807A4

公开(公告)日：2017-08-16

申请号：EP13899973

申请日：2013-12-19

申请人： INTEL CORP

发明人： LEIB JEFFREY S ,  TROEGER RALPH T ,  BERGSTROM DANIEL B

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L21/76895 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/528 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： Techniques and methods related to forming a wrap-around contact on a semiconductor device, and apparatus, system, and mobile platform incorporating such semiconductor devices.

摘要翻译： 涉及在半导体器件上形成环绕式接触的技术和方法，以及包含这种半导体器件的设备，系统和移动平台。

公开(公告)号：EP2663419A2

公开(公告)日：2013-11-20

申请号：EP12704145.7

申请日：2012-01-11

申请人： Tamarack Scientific Co. Inc.

发明人： SOUTER, Matthew E.

IPC分类号： B23K26/06 ,  B23K26/08 ,  H01L21/768

CPC分类号： B23K26/40 ,  B23K26/06 ,  B23K26/0626 ,  B23K26/0853 ,  B23K26/127 ,  B23K26/142 ,  B23K26/1462 ,  B23K26/364 ,  B23K2203/172 ,  H01L21/76865 ,  H01L21/76871

摘要： A method for making conductive traces and interconnects on a surface of a substrate includes, for an embodiment, forming a dielectric or polymer layer on the surface of the substrate, forming a seed layer of an electrically conductive material on the dielectric or polymer layer, patterning a photoresist on the seed layer, forming the conductive traces on the patterned photoresist and seed layer, removing the photoresist from the substrate, and irradiating the surface of the substrate with a fluence of laser light effective to ablate the seed layer from areas of the substrate surface exclusive of the conductive traces.

摘要翻译： 在衬底表面上制造导电迹线和互连的方法包括在衬底的表面上形成电介质层或聚合物层，在电介质层或聚合物层上形成导电材料种子层，构图 在种子层上的光致抗蚀剂，在图案化的光致抗蚀剂和籽晶层上形成导电迹线，从衬底去除光致抗蚀剂，并用激光能量照射衬底的表面，该激光能有效地从衬底的区域烧蚀晶种层 表面排除导电迹线。

公开(公告)号：EP2342743A1

公开(公告)日：2011-07-13

申请号：EP09819613.2

申请日：2009-07-21

申请人： International Business Machines Corporation

发明人： GIGNAC, Lynne, M. ,  HU, Chao-kun ,  MITTAL, Surbhi ,  YANG, Chih-chao

IPC分类号： H01L21/70 ,  H01L21/00

CPC分类号： H01L23/53238 ,  H01L21/02362 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76868 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure including a noble metal-containing cap that is present at least on some portion of an upper surface of at least one conductive material that is embedded within an interconnect dielectric material is provided. In one embodiment, the noble metal-containing cap is discontinuous, e.g., exists as nuclei or islands on the surface of the at least one conductive material. In another embodiment, the noble metal-containing cap has a non-uniform thickness across the surface of the at least one conductive material.

公开(公告)号：EP1936673A4

公开(公告)日：2011-01-05

申请号：EP06811509

申请日：2006-10-10

申请人： HITACHI CHEMICAL CO LTD

发明人： SHINODA TAKASHI ,  NOBE SHIGERU ,  SAKURADA TAKAFUMI ,  OOMORI YOSHIKAZU ,  KIMURA TADAHIRO

IPC分类号： H01L21/321 ,  B24B37/00 ,  C09G1/02 ,  C09K3/14 ,  H01L21/304

CPC分类号： C09G1/02 ,  C23F3/04 ,  H01L21/30625 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76865

摘要： The invention provides polishing slurry for CMP for suppressing corrosion of wiring lines of a conductive substance, or for suppressing bimetallic corrosion of a barrier conductor and conductive substance, by suppressing electrons from being transferred at near the boundaries between a barrier conductor and a conductive substance such as copper. The invention provides polishing slurry for CMP for polishing at least a conductor layer and a conductive substance layer in contact with the conductor layer, wherein the absolute value of the potential difference between the conductive substance and the conductor at 50 ± 5°C is 0.25 V or less in the polishing slurry when a positive electrode and a negative electrode of a potentiometer are connected to the conductive substance and the conductor, respectively. The polishing slurry for CMP preferably comprises at least one compound selected from heterocyclic compounds containing any one of hydroxyl group, carbonyl group, carboxyl group, amino group, amide group and sulfinyl group, and containing at least one of nitrogen and sulfur atoms.

公开(公告)号：EP1366512A4

公开(公告)日：2009-07-08

申请号：EP01987440

申请日：2001-12-19

申请人： IBM

发明人： WALKER GEORGE F ,  GOLDBLATT RONALD D ,  GRUBER PETER A ,  HORTON RAYMOND R ,  PETRARCA KEVIN S ,  VOLANT RICHARD P ,  CHENG TIEN-JEN

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/485 ,  H01L21/44 ,  H01L23/48

CPC分类号： H01L24/48 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00015 ,  H01L2924/00012

摘要： A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

摘要翻译： 描述了用于形成适用于引线键合和焊料凸点倒装芯片连接（例如可控塌陷芯片连接（C4））的公共输入 - 输出（I / O）位置的过程。 本发明特别适用于使用铜作为互连材料的半导体芯片，其中用于制造这种芯片的软电介质容易因结合力而损坏。 本发明通过在衬垫的顶表面上提供具有贵金属的部位，同时提供扩散阻挡层以维持金属互连的高导电性，从而降低了损坏的风险。 通过提供在衬底中形成的特征中选择性地沉积金属层的方法来减少用于在衬底内形成I / O部位的工艺步骤。 由于本发明的I / O站点可以用于引线键合或焊料凸点连接，这为芯片互连选项提供了增加的灵活性，同时还降低了工艺成本。

公开(公告)号：EP1812963A1

公开(公告)日：2007-08-01

申请号：EP05798172.2

申请日：2005-11-02

申请人： Koninklijke Philips Electronics N.V.

发明人： NGUYENHOANG, Viet ,  VERHEIJDEN, Greja, J., A., M.

IPC分类号： H01L21/321 ,  H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76865

摘要： Manufacturing a damascene structure involves: forming a sacrificial layer (20) on a substrate (10) to protect an area around a recess (30) for the damascene structure, forming a barrier layer (40) in the recess, and in electrical contact with the sacrificial layer, forming the damascene structure (50) in the recess, and planarising. During the planarising the sacrificial layer reacts electrochemically with the barrier layer or with the damascene structure. This can alter a relative rate of removal of the damascene structure and the sacrificial layer so as to reduce dishing or protrusion of the damascene structure, and reduce copper residues, and reduce barrier corrosion. The barrier layer can be formed by ALCVD. The barrier material being one or more of WCN and TaN. The sacrificial layer can be TaN, TiN or W.

公开(公告)号：EP1570517A1

公开(公告)日：2005-09-07

申请号：EP03796085.3

申请日：2003-12-08

申请人： International Business Machines Corporation

发明人： CLEVENGER, Larry ,  DALTON, Timothy ,  HOINKIS, Mark ,  KALDOR, Steffen ,  KUMAR, Kaushik ,  LA TULIPE, Douglas, Jr. ,  SEO, Soon-Cheon ,  SIMON, Andrew ,  WANG, Yun-Yu ,  YANG, Chih-Chao ,  YANG, Haining

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865

摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a capping layer (16) and a dielectric layer (18). The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor (14). In the process of sputter etching, the capping layer is redeposited (22) onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

公开(公告)号：EP1442153A1

公开(公告)日：2004-08-04

申请号：EP02778525.2

申请日：2002-10-11

申请人： Epion Corporation

发明人： SKINNER, Wesley, J. ,  HAUTALA, John, J.

IPC分类号： C23C14/32 ,  H01L21/322 ,  H01L23/48

CPC分类号： H01L21/02063 ,  H01J2237/0812 ,  H01J2237/31 ,  H01L21/02046 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76862 ,  H01L21/76865

摘要： Reactive gas cluster ion beam processing using gas cluster ions comprising a mixture of gases cleans and/or etches the bottoms of electrical interconnect vias and/or trenches in integrated circuits(900) to produce interconnect structures(902) with lower contact resistances and better reliability than was previously achieved with conventional processes. In one embodiment, an electrical interconnect via structure (902) uses a dielectric or high resistivity diffusion barrier material (702).

公开(公告)号：EP1102315A3

公开(公告)日：2003-09-24

申请号：EP00640011.3

申请日：2000-11-13

申请人： Chartered Semiconductor Manufacturing Pte Ltd.

发明人： Gupta, Subhash ,  Ho, Kwok Keung Paul ,  Shou, Mei-Sheng ,  Chooi, Simon

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76877

摘要： A new method to prevent copper contamination of the intermetal dielectric layer during via or dual damascene etching by forming a capping layer over the first copper metallization is described. A first copper metallization is formed in a dielectric layer overlying a semiconductor substrate wherein a barrier metal layer is formed underlying the first copper metallization and overlying the dielectric layer. The first copper metallization is planarized, then etched to form a recess below the surface of the dielectric layer. A conductive capping layer is deposited overlying the first copper metallization within the recess and overlying the dielectric layer. The conductive capping layer is removed except over the first copper metallization within the recess using one of several methods. An intermetal dielectric layer is deposited overlying the dielectric layer and the conductive capping layer overlying the first copper metallization. A via or dual damascene opening is etched through the intermetal dielectric layer to the conductive capping layer wherein the conductive capping layer prevents copper contamination of the intermetal dielectric layer during etching. The via or dual damascene opening is filled with a metal layer to complete electrical connections in the fabrication of an integrated circuit device.